DAQ E Series E Series User Manual E Series User Manual February 2007 370503K-01
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Important Information Warranty The E Series devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
Compliance Compliance with FCC/Canada Radio Frequency Interference Regulations Determining FCC Class The Federal Communications Commission (FCC) has rules to protect wireless communications from interference. The FCC places digital electronics into two classes. These classes are known as Class A (for use in industrial commercial locations only) or Class B (for use in residential or commercial locations). All National Instruments (NI) products are FCC Class A products.
Contents About This Manual Conventions ...................................................................................................................xv Related Documentation..................................................................................................xvi NI-DAQ for Windows.....................................................................................xvi NI-DAQmx for Linux......................................................................................xvi NI-DAQmx Base ...
Contents Chapter 2 Analog Input Analog Input Circuitry .................................................................................................. 2-1 Mux ................................................................................................................. 2-1 Instrumentation Amplifier (NI-PGIA) ............................................................ 2-2 A/D Converter................................................................................................. 2-2 AI FIFO........
Contents Differential Connection Considerations ........................................................................2-22 Differential Connections for Ground-Referenced Signal Sources ..................2-23 Common-Mode Signal Rejection Considerations.............................2-24 Differential Connections for Non-Referenced or Floating Signal Sources ................................................................................2-24 Single-Ended Connection Considerations .............................
Contents Chapter 3 Analog Output Analog Output Circuitry................................................................................................ 3-1 DACs............................................................................................................... 3-1 DAC FIFO....................................................................................................... 3-1 AO Sample Clock ...........................................................................................
Contents Chapter 4 Digital I/O Extended Digital I/O ......................................................................................................4-2 Port 3 Signal Assignments...............................................................................4-2 Power-On State................................................................................................4-3 Changing DIO Power-On State to Pulled Low .................................4-3 Timing Specifications...............................
Contents Chapter 7 Digital Routing Timing Signal Routing .................................................................................................. 7-1 Connecting Timing Signals ........................................................................................... 7-4 Routing Signals in Software.......................................................................................... 7-5 Chapter 8 Real-Time System Integration Bus (RTSI) RTSI Triggers...........................................
Contents Appendix B I/O Connector Pinouts Appendix C Troubleshooting Appendix D Technical Support and Professional Services Glossary Index © National Instruments Corporation xiii E Series User Manual
About This Manual The E Series User Manual contains information about using the National Instruments E Series and several B Series data acquisition (DAQ) devices with NI-DAQ 8.0 or later. E Series devices feature up to 64 analog input (AI) channels, two counters, eight or 32 lines of digital input/output (DIO), and up to two analog output (AO) channels. The B Series devices discussed in this document are similar to E Series devices, but do not support SCXI, RTSI, or referenced single-ended AI mode.
About This Manual monospace italic Italic text in this font denotes text that is a placeholder for a word or value that you must supply. Platform Text in this font denotes a specific platform and indicates that the text following it applies only to that platform. Related Documentation Each application software package and driver includes information about writing applications for taking measurements and controlling measurement devices. The following references to documents assume you have NI-DAQ 8.
About This Manual The NI-DAQ Readme for Linux lists supported devices and includes software installation instructions, frequently asked questions, and known issues. The C Function Reference Help describes functions and attributes. The NI-DAQmx for Linux Configuration Guide provides configuration instructions, templates, and instructions for using test panels. Note All NI-DAQmx documentation for Linux is installed at /usr/local/natinst/ NI-DAQmx/docs.
About This Manual programming concepts, step-by-step instructions for using LabVIEW, and reference information about LabVIEW VIs, functions, palettes, menus, and tools. Refer to the following locations on the Contents tab of the LabVIEW Help for information about NI-DAQmx: • Getting Started»Getting Started with DAQ—Includes overview information and a tutorial to learn how to take an NI-DAQmx measurement in LabVIEW using the DAQ Assistant.
About This Manual this help file in Visual Studio. NET, select Measurement Studio» NI Measurement Studio Help. To create an application in Visual C++, Visual C#, or Visual Basic .NET, follow these general steps: 1. In Visual Studio .NET, select File»New»Project to launch the New Project dialog box. 2. Find the Measurement Studio folder for the language you want to create a program in. 3. Choose a project type. You add DAQ tasks as a part of this step.
About This Manual conceptual topics for using NI-DAQmx with Visual C# and Visual Basic .NET. To get to the same help topics from within Visual Studio, go to Help» Contents. Select Measurement Studio from the Filtered By drop-down list and follow the previous instructions. Device Documentation and Specifications NI-DAQmx includes the Device Document Browser, which contains online documentation for supported DAQ and SCXI devices, such as documents describing device pinouts, features, and operation.
DAQ System Overview 1 Figure 1-1 shows a typical DAQ system setup, which includes transducers, signal conditioning, cables that connect the various devices to the accessories, the E Series device, and the programming software. Refer to the Using Accessories with Devices section for a list of devices and their compatible accessories.
Chapter 1 DAQ System Overview 5 6 7 4 3 + V – 2 + HV – + – + mV – 1 1 2 3 4 Sensors and Transducers Terminal Block Accessory SCXI Module SCXI Chassis 5 6 7 Cable Assembly DAQ Device Personal Computer Figure 1-1. DAQ System Overview DAQ Hardware DAQ hardware digitizes signals, performs D/A conversions to generate analog output signals, and measures and controls digital I/O signals. E Series User Manual 1-2 ni.
Chapter 1 DAQ System Overview DAQ-STC E Series devices use the National Instruments DAQ system timing controller (DAQ-STC) for time-related functions. The DAQ-STC consists of the following timing groups. • AI—Two 24-bit, two 16-bit counters • AO—Three 24-bit, one 16-bit counter • General-purpose counter/timer functions—Two 24-bit counters You can independently configure the groups for timing resolutions of 50 ns or 10 μs.
Chapter 1 DAQ System Overview Internal or Self-Calibration Self-calibration is a process to adjust the device relative to a highly accurate and stable internal reference on the device. Self-calibration is similar to the auto-calibration or auto-zero found on some instruments. You should perform a self-calibration whenever environmental conditions, such as ambient temperature, change significantly.
Chapter 1 DAQ System Overview To measure signals from these various transducers, you must convert them into a form that a DAQ device can accept. For example, the output voltage of most thermocouples is very small and susceptible to noise. Therefore, you may need to amplify or filter the thermocouple output before digitizing it. The manipulation of signals to prepare them for digitizing is called signal conditioning. For more information about sensors, refer to the following documents.
Chapter 1 DAQ System Overview SCC SCC is a front-end signal conditioning system for E Series plug-in data acquisition devices. A SCC system consists of a shielded carrier that holds up to 20 single or dual-channel SCC modules for conditioning thermocouples and other transducers. SCC is designed for small measurement systems where you need only a few channels of each signal type, or for portable applications. SCC systems also offer the most comprehensive and flexible signal connectivity options.
Chapter 1 DAQ System Overview • SCXI modules and accessories for isolating, amplifying, exciting, and multiplexing signals for relays and analog output; with SCXI you can condition and acquire up to 3,072 channels • Low-channel-count signal conditioning modules, devices, and accessories, including conditioning for strain gauges and RTDs, simultaneous sample-and-hold circuitry, and relays For more specific information about these products, refer to ni.com.
Chapter 1 DAQ System Overview Table 1-2.
Chapter 1 DAQ System Overview Table 1-3.
Chapter 1 DAQ System Overview connectors used for DAQ devices, refer to the KnowledgeBase document, Specifications and Manufacturers for Board Mating Connectors. Programming Devices in Software National Instruments measurement devices are packaged with NI-DAQ driver software, an extensive library of functions and VIs you can call from your application software, such as LabVIEW or LabWindows/CVI, to program all the features of your NI measurement devices.
Chapter 1 – DAQ System Overview NI-DAQ\Examples\VBasic directory contains the examples not associated with Measurement Studio • NI-DAQmx examples for ANSI C are in the NI-DAQ\Examples\ DAQmx ANSI C Dev directory • Traditional NI-DAQ (Legacy) examples for ANSI C are in the NI-DAQ\Examples\VisualC directory For additional examples, refer to zone.ni.com. I/O Connector Signal Descriptions Table 1-4 describes the signals found on the I/O connectors.
Chapter 1 DAQ System Overview Table 1-4. I/O Connector Signal Descriptions (Continued) Signal Name D GND Reference Direction Description — — Digital Ground—These pins supply the reference for the digital signals at the I/O connector as well as the +5 VDC supply. All three ground references—AI GND, AO GND, and D GND—are connected on the device. P0.<0..7> D GND Input or Output Digital I/O Signals—You can individually configure each signal as an input or output. P0.6 and P0.
Chapter 1 DAQ System Overview Table 1-4. I/O Connector Signal Descriptions (Continued) Signal Name Reference PFI 1/AI REF TRIG, PFI 1 D GND PFI 2/AI CONV CLK D GND PFI 3/CTR 1 SRC D GND PFI 4/CTR 1 GATE D GND CTR 1 OUT D GND PFI 5/AO SAMP CLK D GND PFI 6/AO START TRIG D GND PFI 7/AI SAMP CLK D GND © National Instruments Corporation Direction Description Input PFI 1—As an input, this pin is a PFI.
Chapter 1 DAQ System Overview Table 1-4. I/O Connector Signal Descriptions (Continued) Signal Name PFI 8/CTR 0 SRC Reference D GND PFI 9/CTR 0 GATE D GND CTR 1 OUT D GND FREQ OUT/USER <1..2> D GND Direction Description Input PFI 8—As an input, this pin is a PFI. Output Counter 0 Source Signal—As an output, this pin is the Ctr0Source signal. This signal reflects the actual source connected to the general-purpose Counter 0. Input PFI 9—As an input, this pin is a PFI.
Chapter 1 DAQ System Overview Table 1-5. Terminal Name Equivalents (Continued) Traditional NI-DAQ (Legacy) NI-DAQmx AIGND AI GND AISENSE AI SENSE AISENSE2 AI SENSE 2 AOGND AO GND CONVERT* AI CONV CLK or AI CONV DAC0OUT AO 0 DAC1OUT AO 1 DGND D GND DIO_# P0.# DIO# P0.# DIOA#, DIOB#, DIOC#... P0.#, P1.#, P2.#...
Chapter 1 DAQ System Overview Table 1-5.
2 Analog Input Figure 2-1 shows the analog input circuitry of E Series devices. AI+ AI+ ADC ADC NI-PGIA NI-PGIA Mux Mux AI AI FIFO FIFO AI AI Data Data AI– AI– Analog Analog Trigger Trigger AI AI Timing Timing Signals Signals Figure 2-1. Analog Input Circuitry Block Diagram E Series AI signals include the following signals: AI <0..15>, AI SENSE, and AI GND. The NI 6031E/6033E/6071E devices include AI <16..63> and AI SENSE 2 in addition to the previous list of signals.
Chapter 2 Analog Input Instrumentation Amplifier (NI-PGIA) The NI programmable gain instrumentation amplifier (NI-PGIA) is a measurement and instrument class amplifier that guarantees minimum settling times at all gains. The NI-PGIA can amplify or attenuate an AI signal to ensure that you use the maximum resolution of the ADC. E Series devices use the NI-PGIA to deliver full 16- and 12-bit accuracy when sampling multiple channels at high gains and fast rates.
Chapter 2 Analog Input across the input range. So, for an input range of 0 to 10 V, the voltage of each code of a 16-bit ADC is 10 V – 0 V --------------------------- = 153 μV 16 2 Some E Series devices support both unipolar and bipolar input ranges. A unipolar input range means that the input voltage range is between 0 and Vref, where Vref is a positive reference voltage. A bipolar input range means that the input voltage range is between –Vref and Vref.
Chapter 2 Analog Input Table 2-1. Input Ranges for NI 6020E, NI 6040E, NI 6052E, NI 6062E, and NI 6070E/6071E (Continued) Precision Input Range Gain Polarity Bipolar NI 6040E NI 6052E NI 6062E NI 6070E/ 6071E 4.88 mV 4.88 mV 305 μV 4.88 mV 4.88 mV NI 6020E –10 to +10 V 0.5 –5 to +5 V 1 2.44 mV 2.44 mV 153 μV 2.44 mV 2.44 mV –2.5 to +2.5 V 2 1.22 mV 1.22 mV 76.3 μV 1.22 mV 1.22 mV –1 to +1 V 5 488 μV 488 μV 30.5 μV 488 μV 488 μV –500 to +500 mV 10 244 μV 244 μV 15.
Chapter 2 Analog Input Note You can calibrate NI 6011E and NI 6030E/6031E/6032E/6033E circuitry for either unipolar or bipolar polarity. If you mix unipolar and bipolar channels in the scan list and you are using NI-DAQ, NI-DAQ loads the calibration constants appropriate to the polarity for which AI channel 0 is configured. Table 2-3. Input Ranges for NI 6023E/6024E/6025E and NI 6034E/6035E/6036E Resolution Input Range Gain NI 6023E/6024E/6025E NI 6034E/6035E/6036E –10 to +10 V 0.5 4.
Chapter 2 Analog Input The single-ended input configurations provide up to 16 channels (64 channels on the NI 6031E, NI 6033E, and NI 6071E). The DIFF input configuration provides up to eight channels (32 channels on the NI 6031E, NI 6033E, and NI 6071E). Input modes are programmed on a per channel basis for multi-mode scanning. For example, you can configure the circuitry to scan 12 channels—four differentially-configured channels and eight single-ended channels.
Chapter 2 Analog Input Table 2-5 shows how signals are routed to the NI-PGIA. Table 2-5. NI-PGIA Signal AI Terminal Configuration Signals Routed to the Positive Input of the NI-PGIA Signals Routed to the Negative Input of the NI-PGIA RSE AI <0..15> AI GND NRSE AI <0..15> AI SENSE DIFF AI <0..7> AI <8..15> Reference all signals to ground either at the source or at the DAQ device. If you have a floating source, reference the signal to ground by using RSE mode or DIFF mode with bias resistors.
Chapter 2 Analog Input Dither With 12-bit E Series devices, you can improve resolution by enabling the Gaussian dither generator and averaging acquired samples. Dithering is a feature on all 12-bit E Series devices. When you enable dithering, you add approximately 0.5 LSBrms of white Gaussian noise to the signal to be converted by the ADC. This addition is useful for applications involving averaging to increase device resolution, as in calibration or spectral analysis.
Chapter 2 LSBs 6.0 LSBs 6.0 4.0 4.0 2.0 2.0 0.0 0.0 –2.0 –2.0 –4.0 –4.0 Analog Input –6.0 –6.0 0 100 200 300 400 500 0 a. Dither Disabled; No Averaging 100 200 300 400 500 b. Dither Disabled; Average of 50 Acquisitions LSBs 6.0 LSBs 6.0 4.0 4.0 2.0 2.0 0.0 0.0 –2.0 –2.0 –4.0 –4.0 –6.0 –6.0 0 100 200 300 400 500 0 c. Dither Enabled; No Averaging 100 200 300 400 500 d. Dither Enabled; Average of 50 Acquisitions Figure 2-3.
Chapter 2 Analog Input E Series devices are designed to have fast settling times. Several factors can increase the settling time, which decreases the accuracy of your measurements.
Chapter 2 Analog Input Use Short High-Quality Cabling Using short high-quality cables can decrease several effects that decrease accuracy including crosstalk, transmission line effects, and noise. The capacitance of the cable can also effectively increase the settling time. National Instruments recommends using individually shielded, twisted-pair wires that are 2 m or less to connect AI signals to the device. Refer to the Connecting Analog Input Signals section for more information.
Chapter 2 Analog Input Connect channel 2 to AI GND (or you can use the internal ground signal; refer to Internal Channels for E Series Devices in the NI-DAQmx Help or the LabVIEW 8.x Help. Set the input range of channel 2 to 0–100 mV to match channel 1. Then scan channels in the order: 0, 2, 1. Inserting a grounded channel between signal channels improves settling time because the NI-PGIA adjusts to the new input range setting faster when the input is grounded.
Chapter 2 Analog Input Example 2 If the time relationship between channels is not critical, you can sample from the same channel multiple times and scan less frequently. For example, suppose an application requires averaging 100 points from channel 0 and averaging 100 points from channel 1. You could alternate reading between channels that is, read one point from channel 0, then one point from channel 1, and so on. You also could read all 100 points from channel 0 and then read 100 points from channel 1.
Chapter 2 Analog Input Buffered In a buffered acquisition, data is moved from the DAQ device onboard FIFO memory to a PC buffer using DMA or interrupts before it is transferred to ADE memory. Buffered acquisitions typically allow for much faster transfer rates than non-buffered acquisitions because data is moved in large blocks, rather than one point at a time. For more information, refer to the Data Transfer Methods section of Chapter 9, Bus Interface.
Chapter 2 Analog Input AI Start Trigger Signal You can use the AI Start Trigger (ai/StartTrigger) signal to begin a measurement acquisition. A measurement acquisition consists of one or more samples. If you do not use triggers, you begin a measurement with a software command.
Chapter 2 Analog Input Outputting the AI Start Trigger Signal You can configure the PFI 0/AI START TRIG pin to output the ai/StartTrigger signal. The output pin reflects the ai/StartTrigger signal regardless of what signal you specify as its source. The output is an active high pulse. Figure 2-5 shows the timing behavior of the PFI 0/AI START TRIG pin configured as an output. tw tw = 50 to 100 ns Figure 2-5.
Chapter 2 Analog Input If the buffer becomes full, the DAQ device continuously discards the oldest samples in the buffer to make space for the next sample. You can access this data (with some limitations) before the DAQ device discards it. Refer to the KnowledgeBase document, Can a Pretriggered Acquisition be Continuous?, for more information. When the reference trigger occurs, the DAQ device continues to write samples to the buffer until the buffer contains the desired number of posttrigger samples.
Chapter 2 Analog Input Using a Digital Source To use ai/ReferenceTrigger with a digital source, specify a source and an edge. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information. Also, specify whether the measurement acquisition stops on the rising edge or falling edge of the ai/ReferenceTrigger signal.
Chapter 2 Analog Input The output is an active high pulse. Figure 2-8 shows the timing behavior of the PFI 1/AI REF TRIG pin configured as an output. tw tw = 50 to 100 ns Figure 2-8. PFI 1/AI REF TRIG Timing Behavior The PFI 1/AI REF TRIG pin is configured as an input by default. AI Pause Trigger Signal You can use the AI Pause Trigger (ai/PauseTrigger) signal to pause and resume a measurement acquisition. This signal is not available as an output.
Chapter 2 Analog Input Connecting Analog Input Signals The following sections discuss the types of signal sources, specify the use of single-ended and DIFF measurements, and provide recommendations for measuring both floating and ground-referenced signal sources. Table 2-6 summarizes the recommended input configuration for both types of signal sources. E Series User Manual 2-20 ni.
Chapter 2 Analog Input Table 2-6.
Chapter 2 Analog Input Types of Signal Sources When configuring the input channels and making signal connections, first determine whether the signal sources are floating or ground-referenced. Floating Signal Sources A floating signal source is not connected to the building ground system, but has an isolated ground-reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolators, and isolation amplifiers.
Chapter 2 Analog Input Therefore, half as many DIFF channel pairs are available compared to individual channels. Use DIFF input connections for any channel that meets any of the following conditions: • The input signal is low-level (less than 1 V). • The leads connecting the signal to the device are greater than 3 m (10 ft.). • The input signal requires a separate ground-reference point or return signal. • The signal leads travel through noisy environments.
Chapter 2 Analog Input With this type of connection, the PGIA rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the device ground, shown as Vcm in this figure. Common-Mode Signal Rejection Considerations Ground-referenced signal sources with differential connections to the device are referenced to some ground point with respect to the device.
Chapter 2 Analog Input The previous figure shows two bias resistors connected in parallel with the signal leads of a floating signal source. If you do not use the resistors and the source is truly floating, the source is not likely to remain within the common-mode signal range of the PGIA. The PGIA then saturates, causing erroneous readings. You must reference the source to AI GND.
Chapter 2 Analog Input Single-Ended Connection Considerations A single-ended connection is one in which the device AI signal is referenced to a ground that it can share with other input signals. The input signal connects to the positive input of the PGIA, and the ground connects to the negative input of the PGIA. When every channel is configured for single-ended input, up to 64 AI channels are available.
Chapter 2 Analog Input Single-Ended Connections for Floating Signal Sources (RSE Configuration) Figure 2-11 shows how to connect a floating signal source to a channel configured for RSE mode. AI Floating Signal Source Programmable Gain Instrumentation Amplifier + + Vs – PGIA Input Multiplexers – AI SENSE + Measured Voltage Vm – AIGND I/O Connector Selected Channel in RSE Configuration Figure 2-11.
Chapter 2 Analog Input I/O Connector AI <0..15> GroundReferenced Signal Source + + Vs – Instrumentation Amplifier + PGIA Input Multiplexers CommonMode Noise and Ground Potential AI SENSE AI GND + Vcm – Vm Measured Voltage – – E Series Device Configured in NRSE Mode Figure 2-12.
Chapter 2 Analog Input Configuring AI Modes in Software You can program channels on an E Series device to acquire in different modes, but once a channel mode is specified, it cannot be reused for another mode. For example, to configure AI 0 for DIFF mode and AI 1 for RSE mode, configure AI 0 and AI 8 in DIFF mode and AI 1 and AI GND in RSE mode. In this configuration, AI 8 is not used in a single-ended configuration.
Chapter 2 Analog Input Figure 2-14. NI-DAQmx Create Virtual Channel.vi Analog Input Timing Signals In order to provide all of the timing functionality described throughout this section, the DAQ-STC provides an extremely powerful and flexible timing engine. Figure 2-15 summarizes all of the clock routing and timing options provided by the analog input timing engine.
Chapter 2 Analog Input Channel 0 Channel 1 Convert Period Sample Period Figure 2-16. Interval Sample The ai/ConvertClock signal controls the convert period, which is determined by the following equation: 1/convert period = convert rate NI-DAQmx chooses the default convert rate to allow for the maximum settling time between conversions. Typically, this rate is the sampling rate for the task multiplied by the number of channels in the task.
Chapter 2 Analog Input An acquisition with pretrigger data allows you to view data that is acquired before the trigger of interest, in addition to data acquired after the trigger. Figure 2-18 shows a typical pretrigger DAQ sequence. The ai/StartTrigger signal can be either a hardware or software signal. If ai/StartTrigger is set up to be a software start trigger, an output pulse appears on the AI START TRIG line when the acquisition begins.
Chapter 2 Analog Input Using a Digital Source To use ai/StartTrigger with a digital source, specify a source and an edge. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information. Also, specify whether the measurement acquisition begins on the rising edge or falling edge of the ai/StartTrigger signal.
Chapter 2 Analog Input The output is an active high pulse. Figure 2-20 shows the timing behavior of the PFI 0/AI START TRIG pin configured as an output. tw tw = 50 to 100 ns Figure 2-20. PFI 0/AI START TRIG Timing Behavior The PFI 0/AI START TRIG pin is configured as an input by default. When acquisitions use a start trigger without a reference trigger, they are posttrigger acquisitions because data is acquired only after the trigger.
Chapter 2 Analog Input When the reference trigger occurs, the DAQ device continues to write samples to the buffer until the buffer contains the desired number of posttrigger samples. Figure 2-21 shows the final buffer. Reference Trigger Post-Trigger Samples Pre-Trigger Samples Complete Buffer Figure 2-21. Reference Trigger Final Buffer Using a Digital Source To use ai/ReferenceTrigger with a digital source, specify a source and an edge.
Chapter 2 Analog Input Using an Analog Source When you use an analog trigger source, the acquisition stops on the first rising edge of the Analog Comparison Event signal. Refer to Chapter 10, Triggering, for more information on analog triggering. Outputting the AI Reference Trigger Signal You can configure the PFI 1/AI REF TRIG pin to output the ai/ReferenceTrigger signal. The output pin reflects the ai/ReferenceTrigger signal regardless of what signal you specify as its source.
Chapter 2 Analog Input Using an Analog Source When you use an analog trigger source, the internal sample clock pauses when the Analog Comparison Event signal is low and resumes when the signal goes high (or vice versa). Refer to Chapter 10, Triggering, for more information on analog triggering. Note Pause triggers are only sensitive to the level of the source, not the edge. AI Sample Clock Signal You can use the AI Sample Clock (ai/SampleClock) signal to initiate a set of measurements.
Chapter 2 Analog Input tw Rising-Edge Polarity Falling-Edge Polarity tw = 10 ns minimum Figure 2-24. ai/SampleClock Timing Requirements Outputting the AI Sample Clock Signal You can configure the PFI 7/AI SAMP CLK pin to output the ai/SampleClock signal. The output pin reflects the ai/SampleClock signal regardless of what signal you specify as its source. You specify the output to have one of two behaviors.
Chapter 2 Analog Input ai/StartTrigger ai/ConvertClock ai/SampleClock toff = 10 ns minimum toff b. Level Behavior. Two Conversions per Sample. Figure 2-26. ai/SampleClock Output The PFI 7/AI SAMP CLK pin is configured as an input by default. Other Timing Requirements A counter on your device internally generates ai/SampleClock unless you select some external source. The ai/StartTrigger signal starts this counter.
Chapter 2 Analog Input Figure 2-27 shows the relationship of the ai/SampleClock signal to the ai/StartTrigger signal. ai/SampleClockTimebase ai/StartTrigger ai/SampleClock Delay From Start Trigger Figure 2-27. ai/SampleClock and ai/StartTrigger AI Sample Clock Timebase Signal Any PFI can externally input the AI Sample Clock Timebase (ai/SampleClockTimebase) signal, which is not available as an output on the I/O connector.
Chapter 2 Analog Input AI Convert Clock Signal You can use the AI Convert Clock (ai/ConvertClock) signal to initiate a single A/D conversion on a single channel. A sample (controlled by the AI Sample Clock) consists of one or more conversions. You specify either an internal or external signal as the source of ai/ConvertClock. You also specify whether the measurement sample begins on the rising edge or falling edge of the ai/ConvertClock signal.
Chapter 2 Analog Input Using an External Source You can use a signal connected to any PFI or RTSI <0..6> pin as the source of ai/ConvertClock. Figure 2-29 shows the timing requirements of the ai/ConvertClock source. tw Rising-Edge Polarity Falling-Edge Polarity tw = 10 ns minimum Figure 2-29. ai/ConvertClock Source Timing Requirements Outputting the AI Convert Clock Signal You can configure the PFI 2/AI CONV CLK pin to output the ai/ConvertClock signal.
Chapter 2 Analog Input Using a Delay from Sample Clock to Convert Clock When using an internally generated ai/ConvertClock, you can also specify a configurable delay from the ai/SampleClock to the first ai/ConvertClock pulse within the sample. By default, this delay is two ticks of the ai/ConvertClockTimebase signal. Figure 2-31 shows the relationship of the ai/SampleClock signal to the ai/ConvertClock signal.
Chapter 2 Analog Input ai/SampleClock ai/ConvertClock 1 2 3 Sample Clock too fast for Convert Clock. Sample Clock pulses are gated off. ai/SampleClock ai/ConvertClock 1 2 3 Convert Clock too fast for Sample Clock. Convert Clock pulses are gated off. ai/SampleClock ai/ConvertClock 1 2 3 Improperly matched Sample Clock and Convert Clock. Leads to aperiodic sampling. ai/SampleClock ai/ConvertClock 1 2 3 Properly matched Sample Clock and Convert Clock. Figure 2-32.
Chapter 2 Analog Input AI Convert Clock Timebase Signal Either the ai/SampleClockTimebase or the MasterTimebase signal can serve as the source of the AI Convert Clock Timebase signal (ai/ConvertClockTimebase), which is not available as an output on the I/O connector. The ai/ConvertClockTimebase is divided down to provide the Onboard Clock source for the ai/ConvertClock.
Chapter 2 Analog Input AI Hold Complete Event Signal AI Hold Complete Event (ai/HoldCompleteEvent) is an output-only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A/D conversion begins. The polarity of this output is software-selectable, but is typically configured so that a low-to-high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed.
Chapter 2 Analog Input Getting Started with AI Applications in Software You can use the E Series device in the following analog input applications: • Single-Point Analog Input • Finite Analog Input • Continuous Analog Input You can perform these applications through DMA, interrupt, or programmed I/O data transfer mechanisms. Some of the applications also use start, reference, and pause triggers.
3 Analog Output Figure 3-1 shows the analog output circuitry of E Series devices. AO 0 DAC0 AO FIFO AO 1 AO Data DAC1 AO Sample Clock Polarity Select Reference Select Figure 3-1. Analog Output Block Diagram Many E Series boards have analog output functionality. E Series boards that support analog output have two AO channels that are controlled by a single clock and are capable of waveform generation.
Chapter 3 Analog Output AO Sample Clock The DAC reads a sample from the FIFO with every cycle of the AO Sample Clock signal and generates the AO voltage. Polarity and Reference Selection Polarity and reference selection allow you to set the AO range. Refer to Table 3-1 to set the range for your device. Refer to the Polarity Selection and the Reference Selection sections for more information. Table 3-1.
Chapter 3 Analog Output Polarity Selection (NI 6020E, NI PXI-6030E, NI PCI-6031E, NI PXI-6040E, NI 6052E, PCI-MIO-16E-4, and PCI-MIO-16XE-10 Devices Only) With these devices, you can configure each AO channel for either unipolar or bipolar output. All other E Series devices are configured for bipolar output only. A unipolar configuration has a range of 0 to Vref at the analog output. A bipolar configuration has a range of –Vref to +Vref at the analog output.
Chapter 3 Analog Output AO Data Generation Methods When performing an analog output operation, there are several different data generation methods available. You can either perform software-timed or hardware-timed generations. Hardware-timed generations can be non-buffered or buffered. Software-Timed Generations With a software-timed generation, software controls the rate at which data is generated. Software sends a separate command to the hardware to initiate each DAC conversion.
Chapter 3 Analog Output Finite sample mode generation refers to the generation of a specific, predetermined number of data samples. Once the specified number of samples has been written out, the generation stops. Continuous generation refers to the generation of an unspecified number of samples. Instead of generating a set number of data samples and stopping, a continuous generation continues until you stop the operation.
Chapter 3 Analog Output AO Start Trigger Signal You can use the AO Start Trigger (ao/StartTrigger) signal to initiate a waveform generation. If you do not use triggers, you begin a generation with a software command. Using a Digital Source To use ao/StartTrigger, specify a source and an edge. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several internal signal on your DAQ device.
Chapter 3 Analog Output The output is an active high pulse. Figure 3-3 shows the timing behavior of the PFI 6/AO START TRIG pin configured as an output. tw tw = 25 to 50 ns Figure 3-3. PFI 6/AO START TRIG Timing Behavior The PFI 6/AO START TRIG pin is configured as an input by default. AO Pause Trigger Signal You can use the AO Pause trigger signal (ao/PauseTrigger) to mask off samples in a DAQ sequence. That is, when ao/PauseTrigger is active, no samples occur.
Chapter 3 Analog Output Connecting Analog Output Signals The AO signals are AO 0, AO 1, and AO GND. AO 0 is the voltage output signal for AO channel 0. AO 1 is the voltage output signal for AO channel 1. AO GND is the ground reference signal for both AO channels and the external reference signal. Figure 3-4 shows how to make AO connections to the device. AO 0 Channel 0 + Load V OUT – AO GND – Load V OUT AO 1 Channel 1 + Analog Output Channels I/O Connector E Series Device Figure 3-4.
Chapter 3 Analog Output Waveform Generation Timing Signals There is one AO Sample Clock that causes all AO channels to update simultaneously. Figure 3-5 summarizes the timing and routing options provided by the analog output timing engine. RTSI 7 Master Timebase PFI 0–9, Onboard RTSI 0–6 Clock ao/SampleClock Timebase ÷200 20 MHz Timebase Ctr1InternalOutput PFI 0–9, RTSI 0–6 Onboard Clock ao/SampleClock ÷ Divisor Figure 3-5.
Chapter 3 Analog Output Using an Analog Source When you use an analog trigger source, the waveform generation begins on the first rising edge of the Analog Comparison Event signal. Refer to Chapter 10, Triggering, for more information on analog triggering. Outputting the AO Start Trigger Signal You can configure the PFI 6/AO START TRIG pin to output the ao/StartTrigger signal. The output pin reflects the ao/StartTrigger signal regardless of what signal you specify as its source.
Chapter 3 Analog Output Using an Analog Source When you use an analog trigger source, the samples are paused when the Analog Comparison Event signal is at a high level. Refer to Chapter 10, Triggering, for more information on analog triggering. AO Sample Clock Signal You can use the AO Sample Clock (ao/SampleClock) signal to initiate AO samples. Each sample updates the outputs of all the DACs. The source of the ao/SampleClock signal can be internal or external.
Chapter 3 Analog Output Outputting the AO Sample Clock Signal You can configure the PFI 5/AO SAMP CLK pin to output the ao/SampleClock signal. The output pin reflects the ao/SampleClock signal regardless of what signal you specify as its source. The output is an active high pulse. Figure 3-9 shows the timing behavior of the PFI 5/AO SAMP CLK pin configured as an output. tw tw = 50 to 75 ns Figure 3-9. PFI 5/AO SAMP CLK Timing Behavior The PFI 5/AO SAMP CLK is configured as an input by default.
Chapter 3 Analog Output Figure 3-10 shows the relationship of the ao/SampleClock signal to the ao/StartTrigger signal. ao/SampleClockTimebase ao/StartTrigger ao/SampleClock Delay From Start Trigger Figure 3-10. ao/SampleClock and ao/StartTrigger AO Sample Clock Timebase Signal You can select any PFI or RTSI pin as well as many other internal signals as the AO Sample Clock Timebase (ao/SampleClockTimebase) signal. This signal is not available as an output on the I/O connector.
Chapter 3 Analog Output Figure 3-11 shows the timing requirements for the ao/SampleClockTimebase signal. tp tw tw tp = 50 ns minimum tw = 23 ns minimum Figure 3-11. ao/SampleClockTimebase Signal Timing Requirements The maximum allowed frequency is 20 MHz, with a minimum pulse width of 10 ns high or low. There is no minimum frequency. Unless you select an external source, either the 20MHzTimebase or 100kHzTimebase generates the ao/SampleClockTimebase signal.
Chapter 3 Analog Output Figure 3-12 shows the timing requirements for MasterTimebase. tp tw tw tp = 50 ns minimum tw = 23 ns minimum Figure 3-12.
4 Digital I/O Figure 4-1 shows the DIO circuitry of the E Series device. Protection Data Out Output Enable Data In Protection Data Out Output Enable Data In Figure 4-1. DIO Circuitry Block Diagram E Series devices contain eight lines of DIO (P0.<0..7>) for general-purpose use.
Chapter 4 Digital I/O or output. At system startup and reset, the DIO ports are all high-impedance. The hardware up/down control for general-purpose Counters 0 and 1 are connected onboard to P0.6 and P0.7, respectively. Thus, you can use P0.6 and P0.7 to control the general-purpose counters. The up/down control signals, Counter 0 Up/Down and Counter 1 Up/Down, are input-only and do not affect the operation of the DIO lines. Refer to Chapter 5, Counters, for more information on counters.
Chapter 4 Digital I/O 82C55A configurations as modes, whereas NI-DAQ, LabWindows/CVI, and LabVIEW documentation refers to them as handshaking and no handshaking. Table 4-1. Configuration Terminology and Signal Assignments Configuration Terminology NI 6016 or NI 6025E National Instruments Software Signal Assignments P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.
Chapter 4 Digital I/O voltage across the pull-down resistor above a TTL-low level of 0.4 VDC. Figure 4-2 shows the DIO configuration for high DIO power-on state. +5 V Device 100 k 82C55 Digital I/O Line RL GND Figure 4-2. DIO Configuration for High DIO Power-On State The following steps show how to calculate the value of RL needed to achieve a TTL-low power-on state for a single DIO line. Using the following formula, calculate the largest possible load to maintain a logic low level of 0.
Chapter 4 Digital I/O Table 4-2. Signal Descriptions Name Type Description STB* Input Strobe input—A low signal on this handshaking line loads data into the input latch. IBF Output Input buffer full—A high signal on this handshaking line indicates that data has been loaded into the input latch. A low signal indicates the device is ready for more data. This is an input acknowledge signal.
Chapter 4 Digital I/O Mode 1 Input Timing (NI 6016 and NI 6025E Devices Only) Figure 4-3 and Table 4-3 show timing specifications for an input transfer in mode 1. T1 T2 T4 STB* T7 T6 IBF INTR RD* T3 T5 DATA Figure 4-3. Input Transfer in Mode 1 Timing Specifications Table 4-3.
Chapter 4 Digital I/O Mode 1 Output Timing (NI 6016 and NI 6025E Devices Only) Figure 4-4 and Table 4-4 show timing specifications for an output transfer in mode 1. T3 T3 WR* WR* T4 T4 OBF* OBF* T1 T1 T6 T6 INTR INTR T5 T5 ACK* ACK* DATA DATA T2 T2 Figure 4-4. Output Transfer in Mode 1 Timing Specifications Table 4-4.
Chapter 4 Digital I/O Mode 2 Bidirectional Timing (NI 6016 and NI 6025E Devices Only) Figure 4-5 and Table 4-5 show timing specifications for a bidirectional transfer in mode 2. T1 WR * T6 OBF * INTR T7 ACK * T3 STB * T10 T4 IBF RD * T2 T5 T8 T9 DATA Figure 4-5. Bidirectional Transfer Timing Specifications Table 4-5.
Chapter 4 Digital I/O Power-On States of the PFI and DIO Lines At system startup and reset, the hardware sets both the PFI and digital lines to high-impedance. This setting means that the device circuitry is not actively driving the output either high or low. However, these lines might have pull-up or pull-down resistors connected to them, as shown in the I/O Terminal Summary table in the specifications of each device. These resistors weakly pull the output to either a logic high or logic low state.
Chapter 4 Digital I/O +5 V LED P0.<4..7> TTL Signal P0.<0..3> +5 V Switch D GND I/O Connector E Series Device Figure 4-6. P0.<0..3> Configured for Digital Input, P0.<4..7> Configured for Digital Output Caution Exceeding the maximum input voltage ratings, which are listed in the I/O Terminal Summary table in the specifications document for each E Series family, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections.
5 Counters Figure 5-1 shows a counter on the E Series device. Source Out Gate Software Registers Figure 5-1. Counter Block Diagram Counters 0 and 1 each have two inputs (source and gate), one output, and two software registers, which are used to perform different operations. Counter functionality is built into the DAQ-STC. Counter Triggering Counters support two different triggering actions: start and pause. A digital trigger can directly initiate these actions.
Chapter 5 Counters Pause Trigger You can use pause triggers in edge counting and continuous pulse generation applications. For edge counting acquisitions, the counter stops counting edges while the external trigger signal is low and resumes when the signal goes high or vice versa. For continuous pulse generations, the counter stops generating pulses while the external trigger signal is low and resumes when the signal goes high or vice versa.
Chapter 5 Counters source edge, as shown by tgsu and tgh. The gate signal is not required after the active edge of the source signal. If you use an internal timebase clock, you cannot synchronize the gate signal with the clock. In this case, gates applied close to a source edge take effect either on that source edge or on the next one. This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources.
Chapter 5 Counters The maximum allowed frequency is 20 MHz, with a minimum pulse width of 10 ns high or low. There is no minimum frequency. For most applications, unless you select an external source, the 20MHzTimebase signal or the 100kHzTimebase signal generates the Ctr0Source signal. Counter 0 Gate Signal You can select any PFI as well as many other internal signals like the Counter 0 Gate (Ctr0Gate) signal.
Chapter 5 Counters Counter 0 Internal Output Signal The Counter 0 Internal Output (Ctr0InternalOutput) signal is the output of Counter 0. This signal reflects the terminal count (TC) of Counter 0. The counter generates a terminal count when its count value rolls over. The two software-selectable output options are pulse on TC and toggle output polarity on TC. The output polarity is software-selectable for both options. Figure 5-5 shows the behavior of the Ctr0InternalOutput signal.
Chapter 5 Counters CTR 0 OUT Pin When the CTR 0 OUT pin is configured as an output, the Ctr0InternalOutput signal drives the pin. As an input, CTR 0 OUT can drive any of the RTSI <0..6> signals. CTR 0 OUT is set to high-impedance at startup. Figure 5-6 shows the relationship of CTR 0 OUT and Ctr0InternalOutput. Can Drive RTSI <0..6>, ai/SampleClock, ai/StartTrigger, or other signals Ctr0Gate Counter 0 Ctr0InternalOutput CTR 0 OUT Ctr0Source Ctr0Up/Down Ctr0Out Can Drive RTSI <0..6> Figure 5-6.
Chapter 5 Counters Figure 5-7 shows the timing requirements for the Ctr1Source signal. tp tw tw tp = 50 ns minimum tw = 10 ns minimum Figure 5-7. Ctr1Source Signal Timing Requirements The maximum allowed frequency is 20 MHz, with a minimum pulse width of 10 ns high or low. There is no minimum frequency. For most applications, unless you select an external source, the 20MHzTimebase signal or the 100kHzTimebase signal generates the Ctr1Source signal.
Chapter 5 Counters Figure 5-8 shows the timing requirements for the Ctr1Gate signal. tw Rising-Edge Polarity Falling-Edge Polarity tw = 10 ns minimum Figure 5-8. Ctr1Gate Signal Timing Requirements Counter 1 Internal Output Signal The Counter 1 Internal Output (Ctr1InternalOutput) signal is the output of Counter 1. This signal reflects the terminal count (TC) of Counter 1. The counter generates a terminal count when its count value rolls over.
Chapter 5 Counters • Ctr1InternalOutput drives the CTR 1 OUT pin to trigger or control external devices. • Ctr1InternalOutput can drive other internal signals. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information. Counter 1 Up/Down Signal You can externally input this signal on the P0.7 pin, but it is not available as an output on the I/O connector.
Chapter 5 Counters Figure 5-10 shows the timing requirements for MasterTimebase. tp tw tw tp = 50 ns minimum tw = 23 ns minimum Figure 5-10. MasterTimebase Timing Requirements Getting Started with Counter Applications in Software You can use the E Series device in the following counter-based applications.
Programmable Function Interfaces (PFI) 6 The 10 Programmable Function Interface (PFI) pins allow timing signals to be routed to and from the I/O connector of a device. Inputs An external timing signal can be input on any PFI pin and multiple timing signals can simultaneously use the same PFI pin. This flexible routing scheme reduces the need to change the physical connections to the I/O connector for different applications.
Chapter 6 Programmable Function Interfaces (PFI) Not all timing signals can be output. PFI pins are labeled with the timing signal that can be output on it. For example, PFI 8 is labeled PFI 8/CTR 0 Source.
7 Digital Routing The digital routing circuitry manages the flow of data between the bus interface and the acquisition subsystems (analog input circuitry, digital I/O and the counters). The digital routing circuitry uses FIFOs (if present) in each subsystem to ensure efficient data movement. The digital routing circuitry also routes timing and control signals. The acquisition subsystems use these signals to manage acquisitions.
Chapter 7 Digital Routing • AO Start Trigger Signal • AO Sample Clock Signal • AO Pause Trigger Signal • AO Sample Clock Timebase Signal • Counter 0 Source Signal • Counter 0 Gate Signal • Counter 0 Up/Down Signal • Counter 1 Source Signal • Counter 1 Gate Signal • Counter 1 Up/Down Signal • Master Timebase Signal You also can control these timing signals by signals generated internally to the DAQ-STC, and these selections are fully software-configurable.
Chapter 7 Digital Routing RTSI Trigger <0..6> ai/ConvertClock PFI <0..9> Onboard Clock Ctr0InternalOutput Figure 7-1. ai/ConvertClock Signal Routing Figure 7-1 shows that ai/Convert Clock can be generated from a number of sources, including the external signals RTSI <0..6> (PCI and PXI buses only) and PFI <0..9> and the internal signals, Onboard Clock and Ctr0InternalOutput. On PCI and PXI devices, many of these timing signals are also available as outputs on the PFI pins.
Chapter 7 Digital Routing Connecting Timing Signals Caution Exceeding the maximum input voltage ratings, which are listed in the I/O Terminal Summary table in the specifications document for each E Series family, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections. The 10 PFI pins labeled PFI <0..9> route all external control over the timing of the device. These lines serve as connections to virtually all internal timing signals.
Chapter 7 Digital Routing PFI 0 PFI 2 PFI 0 Source PFI 2 Source D GND I/O Connector E Series Device Figure 7-2. Connecting Timing Signals Routing Signals in Software Table 7-1 lists the basic functions you can use to route signals. Table 7-1. Functions For Routing Signals. Language LabVIEW C Program Function NI-DAQmx DAQmx Export Signal.vi and DAQmx Connect Terminals.vi Traditional NI-DAQ (Legacy) Route Signal.
Real-Time System Integration Bus (RTSI) 8 NI-DAQ devices use the Real-Time System Integration (RTSI) bus to easily synchronize several measurement functions to a common trigger or timing event. In a PCI system, the RTSI bus consists of the RTSI bus interface and a ribbon cable. The bus can route timing and trigger signals between several functions on as many as five DAQ devices in the computer.
Chapter 8 Real-Time System Integration Bus (RTSI) DAQ-STC ai/ConvertClock ai/StartTrigger ai/ReferenceTrigger ao/SampleClock ao/StartTrigger Ctr0Gate RTSI Switch RTSI Bus Connector Ctr0Source Trigger <0..6> Ctr0InternalOutput Ctr0Out ai/SampleClock ai/PauseTrigger ai/SampleClockTimebase ao/SampleClockTimebase Ctr1Source Ctr1Gate ao/PauseTrigger RTSI Trigger 7 20MHz Timebase Switch Master Timebase Figure 8-1.
Chapter 8 Real-Time System Integration Bus (RTSI) plugged into Slot 2 of the chassis. E Series devices can accept timing signals from the PXI star trigger line, but they cannot drive signals onto it. For more information about the star trigger, refer to the PXI Hardware Specification Revision 2.1. DAQ-STC ai/ConvertClock ai/StartTrigger ai/ReferenceTrigger ao/SampleClock ao/StartTrigger PXI Star 6 Ctr0Gate RTSI Switch PXI Bus Connector Ctr0Source PXI Trigger <0..
Chapter 8 Real-Time System Integration Bus (RTSI) Device and RTSI Clocks Many E Series device functions require a frequency timebase to generate the necessary timing signals for controlling A/D conversions, DAC updates, or general-purpose signals at the I/O connector. This timebase is also called the Master Timebase or Onboard Clock. Refer to the Master Timebase Signal section of Chapter 5, Counters, for more information.
9 Bus Interface Each E Series device is designed on a complete hardware architecture that is deployed on one of the following platforms: • PCI • PXI • PCMCIA (DAQCard) • USB (DAQPad) • IEEE 1394 (DAQPad) Using NI-DAQ driver software, you have the flexibility to change hardware platforms and operating systems with little or no change to software code. MITE and DAQPnP PCI and PXI E Series devices use the MITE application-specific integrated circuit (ASIC) as a bus master interface to the PCI bus.
Chapter 9 Bus Interface standard implementation for CompactPCI does not include these sub-buses. The PXI E Series device works in any standard CompactPCI chassis adhering to the PICMG CompactPCI 2.0 R3.0 core specification. PXI-specific features are implemented on the J2 connector of the CompactPCI bus. The PXI device is compatible with any CompactPCI chassis with a sub-bus that does not drive the lines used by that device.
Chapter 9 Bus Interface Changing Data Transfer Methods between DMA and IRQ There are a limited number of DMA channels per device. Refer to Appendix A, Device-Specific Information, for the specifications document for your device. Each operation (for example, AI, AO, and so on) that requires a DMA channel uses that method until all of the DMA channels are used. Once all of the DMA channels are used, you will get an error if you try to run another operation requesting a DMA channel.
10 Triggering A trigger is a signal that causes a device to perform an action, such as starting an acquisition. You can program your DAQ device to generate triggers on the following: • A software command • A condition on an external digital signal • A condition on an external analog signal You can also program your DAQ device to perform an action in response to a trigger.
Chapter 10 Triggering Figure 10-1 shows a falling-edge trigger. 5V Digital Trigger 0V Falling edge initiates acquisition Figure 10-1. Falling-Edge Trigger You can also program your DAQ device to perform an action in response to a trigger from a digital source. This action can affect the following: • Analog input acquisitions • Analog output generation • Counter behavior Triggering with an Analog Source Some E Series devices can generate a trigger on an analog signal.
Chapter 10 Triggering PFI 0/AI START TRIG Pin This pin is an analog input when configured as an analog trigger. Therefore, it is susceptible to crosstalk from adjacent pins, resulting in false triggering when the pin is unconnected. To avoid false triggering, ensure that this pin is connected to a low-impedance signal source (less than 1 kΩ source impedance) if you plan to enable this input using the application software. Analog Input Channel You can select any analog input channel to drive the PGIA.
Chapter 10 Triggering Analog Trigger Types You can configure the analog trigger circuitry to different triggering modes. Refer to the Triggering with an Analog Source section for more information. Level Triggering You can configure the analog trigger circuitry to detect when the analog signal is below or above a level you specify. In below-level analog triggering mode, the trigger is generated when the signal value is less than Level, as shown in Figure 10-3. Level Analog Comparison Event Figure 10-3.
Chapter 10 Triggering Level Triggering with Hysteresis Hysteresis adds a programmable window above or below the trigger level that a valid trigger signal must pass through and is often used to reduce false triggering due to noise or jitter in the signal. When using Hysteresis with a rising slope, the trigger asserts when the signal starts below Level and then crosses above Level. The trigger deasserts when the signal crosses below Level minus hysteresis as shown in Figure 10-5.
Chapter 10 Triggering Figure 10-7 demonstrates a trigger that asserts when the signal enters the window. Top Bottom Analog Comparison Event Figure 10-7. Window Triggering Analog Trigger Accuracy The analog trigger circuitry compares the voltage of the trigger source to the output of programmable trigger DACs. When you configure the level (or the high and low limits in window trigger mode), the device adjusts the output of the trigger DACs.
A Device-Specific Information This appendix includes device- and family-specific information about the following E Series device families: Note • NI 6011E (NI PCI-MIO-16XE-50) • NI 6013/6014 Family • NI 6015/6016 Family • NI 6020E Family • NI 6023E/6024E/6025E Family • NI 6030E/6031E/6032E/6033E Family • NI 6034E/6035E/6036E Family • NI 6040E Family • NI 6052E Family • NI DAQCard-6062E • NI 6070E/6071E Family To obtain documentation for devices not listed here, refer to ni.
Appendix A Device-Specific Information NI 6011E (NI PCI-MIO-16XE-50) Dither You cannot disable dither on the NI 6011E (NI PCI-MIO-16XE-50). The ADC resolution on this device is so fine that the ADC and the PGIA inherently produce almost 0.5 LSBrms of noise. This configuration is equivalent to having a dither circuit that is always enabled. NI 6011E (NI PCI-MIO-16XE-50) Block Diagram Figure A-1 shows a block diagram of the NI 6011E (NI PCI-MIO-16XE-50).
Appendix A Device-Specific Information NI 6011E (NI PCI-MIO-16XE-50) Specifications Refer to the NI PCI-MIO-16XE-50 (NI 6011E) Specifications for more detailed information on the device. NI 6011E (NI PCI-MIO-16XE-50) Pinout Figure A-2 shows the NI 6011E (NI PCI-MIO-16XE-50) device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND AO EXT REF P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI 6013/6014 Family The NI 6013/6014 are basic multifunction AI, AO, DIO, and TIO devices for PCI bus computers.
Appendix A Device-Specific Information NI 6013/6014 Block Diagram Figure A-3 shows a block diagram of the NI 6013/6014.
Appendix A AI 8 AI 1 AI GND AI 10 AI 3 AI GND AI 4 AI GND AI 13 AI 6 AI GND AI 15 NC NC NC P0.4 D GND P0.1 P0.
Appendix A Device-Specific Information NI 6014 Pinout Figure A-5 shows the NI 6014 device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names. E Series User Manual A-8 ni.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND NC P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI 6015/6016 Family The DAQPad-6015/6016 are Plug-and-Play, USB-compatible multifunction AI, AO, DIO, and TIO devices for USB-compatible computers. The DAQPad-6015/6016 family of devices features the following: • 16 AI channels (eight differential) with 16-bit resolution • Two AO channels with 16-bit resolution • (DAQPad-6015) Eight lines of TTL-compatible DIO. • (DAQPad-6016) 32 lines of TTL-compatible DIO.
Appendix A Device-Specific Information Table A-1. NI DAQPad-6015/6016 Versions Model I/O Connector Form Factor DAQPad-6015: 64 screw terminals DAQPad-6016: 96 screw terminals Prototyping areas (8.0 in. × 6.75 in. × 1.4 in.) Stackable Integrated strain relief A removable lid DAQPad-6015 BNC Eight AI BNCs Two AO BNCs Four digital BNCs A spring-loaded Combicon connector for other digital signals (12.1 in. × 10 in. × 1.7 in.
Appendix A Device-Specific Information DAQPad-6015/6016 Block Diagram Figure A-6 shows a block diagram of the DAQPad-6015/6016.
Appendix A Device-Specific Information Connecting Signals to the NI DAQPad-6015 BNC Analog Input You can use each analog input BNC connector for one differential signal or two single-ended signals. Differential Signals To connect differential signals, determine the type of signal source you are using: a floating signal source or a ground-referenced signal source.
Appendix A Device-Specific Information AI x + AI x – GS FS 0.1 µF 5 kΩ AI GND Figure A-8. BNC DAQPad Analog Input Circuitry Single-Ended Signals For each BNC connector that you use for two single-ended channels, set the source type switch to the GS position. This setting disconnects the built-in ground reference resistor from the negative terminal of the BNC connector, allowing the connector to be used as a single-ended channel, as shown in Figure A-9. AI x + 8 AI x GS FS 0.
Appendix A Device-Specific Information Analog Output You can access analog output signals on the BNC connectors labeled AO 0 and AO 1. Figure A-10 shows the analog output circuitry on BNC DAQPads. AO AO GND Figure A-10. BNC DAQPads Analog Output Circuitry Refer to the Connecting Analog Output Signals section of Chapter 3, Analog Output, for more information.
Appendix A Device-Specific Information User <1..2> The User <1..2> signals connect directly from a screw terminal to a BNC. They allow you to use a BNC connector for a digital or timing I/O signal of your choice. The USER 1 BNC is internally connected to pin 21 and the USER 2 BNC is internally connected to pin 22 on the 30-pin I/O connector. Figure A-13 shows the connection of the User <1..2> BNCs. User 1 BNC Pin 21 User 2 BNC D GND 30-Pin I/O Connector D GND Pin 22 Figure A-13. User <1..
Appendix A Device-Specific Information Other Signals You can access other signals on BNC DAQPads through a 30-pin Combicon connector. To connect to one of these signals, use a small screwdriver to press down the orange spring release button at a terminal and insert a wire. Releasing the orange spring release button will lock the wire securely in place. You can remove the Combicon plugs to assist in connecting wires.
Appendix A Device-Specific Information DAQPad-6015/6016 LED Patterns The DAQPad-6015/6016 devices have two LEDs labeled ACTIVE and READY. The ACTIVE LED indicates activity over the bus. The READY LED indicates whether or not the device is configured. The DAQPad-6015 BNC and mass termination devices have a READY LED only. Table A-2 shows the behavior of the LEDs. Table A-2. LEDs Behavior ACTIVE READY Off Off The device is not powered.
Appendix A Device-Specific Information Replacing the DAQPad-6015/6016 Fuse The DAQPad-6015/6016 devices have a replaceable F 2 A 250 V (5 × 20 mm) fuse. To remove the fuse from the DAQPad-6015/6016, loosen the four flathead Phillips screws that attach the back lid to the enclosure, and remove the lid as shown in Figure A-16. The fuse is located between the power connector and switch near the back of the device.
Appendix A Device-Specific Information Figure A-17. DAQPad-6015 Mass Termination Device DAQPad-6015/6016 Specifications Refer to the NI DAQPad-6015/6016 Family Specifications for more detailed information on the devices. E Series User Manual A-20 ni.
Appendix A Device-Specific Information NI DAQPad-6015 Pinout Figure A-18 shows the NI DAQPad-6015 device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names. Digital and Timing Analog P0.0 33 49 CTR 0 OUT AI 0 1 17 AI 4 P0.
Appendix A Device-Specific Information NI DAQPad-6015 BNC Pinout Figure A-19 shows the NI DAQPad-6015 BNC device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND NC P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI DAQPad-6016 Pinout Figure A-21 shows the NI DAQPad-6016 device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names. Figure A-21.
Appendix A Note Device-Specific Information The BNC version of the DAQPad-6020E has a 30-pin I/O connector. Because the DAQPad-6020E has no DIP switches, jumpers, or potentiometers, you can easily configure and calibrate it through software. There are three versions of the DAQPad-6020E offering different I/O connectivity and form factors. These versions are illustrated in Table A-3. Table A-3.
Appendix A Device-Specific Information DAQPad-6020E Block Diagram Figure A-22 shows a block diagram of the DAQPad-6020E.
Appendix A Device-Specific Information position. Figure A-23 shows the source type switch locations on the front panel of the BNC DAQPads.
Appendix A Device-Specific Information Single-Ended Signals For each BNC connector that you use for two single-ended channels, set the source type switch to the GS position. This setting disconnects the built-in ground reference resistor from the negative terminal of the BNC connector, allowing the connector to be used as a single-ended channel, as shown in Figure A-25. AI x + 8 AI x GS FS 0.1 µF 5 kΩ AI GND Figure A-25.
Appendix A Device-Specific Information Refer to the Connecting Analog Output Signals section of Chapter 3, Analog Output, for more information. AO External Reference The AO EXT REF input controls the voltage range of analog output signals. Figure A-27 shows circuitry of the AO EXT REF on BNC DAQPads. AO EXT REF AI GND Figure A-27. AO EXT REF Refer to the Reference Selection section of Chapter 3, Analog Output, for more information.
Appendix A Device-Specific Information User <1..2> The User <1..2> signals connect directly from a screw terminal to a BNC. They allow you to use a BNC connector for a digital or timing I/O signal of your choice. The USER 1 BNC is internally connected to pin 21 and the USER 2 BNC is internally connected to pin 22 on the 30-pin I/O connector. Figure A-30 shows the connection of the User <1..2> BNCs. User 1 BNC Pin 21 User 2 BNC D GND 30-Pin I/O Connector D GND Pin 22 Figure A-30. BNC User <1..
Appendix A Device-Specific Information Other Signals You can access other signals on BNC DAQPads through a 30-pin Combicon connector. To connect to one of these signals, use a small screwdriver to press down the orange spring release button at a terminal and insert a wire. Releasing the orange spring release button will lock the wire securely in place. You can remove the Combicon plugs to assist in connecting wires.
Appendix A Device-Specific Information DAQPad-6020E LED Patterns The DAQPad-6020E has an LED on the front panel. Refer to Table A-4 for descriptions of each LED state. Table A-4. DAQPad-6020E LEDs LED On DAQPad-6020E State The device is configured. Dim — Off The device turns off or goes into the low-power, suspend mode when the computer is powered down. 1 blink The device is recognized but not configured.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND AO EXT REF P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI DAQPad-6020E BNC Pinout Figure A-34 shows the NI DAQPad-6020E BNC device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information NI 6023E/6024E/6025E Family The NI 6023E/6024E/6025E are high-performance multifunction AI, AO, DIO, and TIO devices for PCI, PXI, PCMCIA, and CompactPCI bus computers.
Appendix A Device-Specific Information NI 6023E/6024E/6025E Block Diagrams Figure A-35 shows a block diagram of the NI PCI-6023E/6024E/6025E and the NI PXI-6025E.
Appendix A Device-Specific Information Figure A-36 shows the block diagram of the DAQCard-6024E.
Appendix A Device-Specific Information AI 8 AI 1 AI GND AI 10 AI 3 AI GND AI 4 AI GND AI 13 AI 6 AI GND AI 15 NC NC NC P0.4 D GND P0.1 P0.
Appendix A Device-Specific Information NI 6024E Pinout Figure A-38 shows the NI 6024E device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND NC P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI 6025E Pinout Figure A-39 shows the NI 6025E device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information AI GND AI GND AI 0 AI 8 AI 1 AI 9 AI 2 AI 10 AI 3 AI 11 AI 4 AI 12 AI 5 AI 13 AI 6 AI 14 AI 7 AI 15 AI SENSE AO 0 AO 1 NC AO GND D GND P0.0 P0.4 P0.1 P0.5 P0.2 P0.6 P0.3 P0.
Appendix A Device-Specific Information For a detailed description of each signal, refer to the I/O Connector Signal Descriptions section of Chapter 1, DAQ System Overview. NI 6030E/6031E/6032E/6033E Family The NI 6030E/6031E/6032E/6033E are Plug-and-Play, multifunction AI, AO, DIO, and TIO devices for PCI bus computers.
Appendix A Device-Specific Information NI 6030E/6031E/6032E/6033E Dither You cannot disable dither on the NI 6030E/6031E/6032E/6033E. The ADC resolution is so fine that the ADC and the PGIA inherently produce almost 0.5 LSBrms of noise. This configuration is equivalent to having a dither circuit that is always enabled. NI 6030E/6031E/6032E/6033E Block Diagrams Figure A-40 shows a block diagram of the NI 6030E/6031E.
Appendix A Device-Specific Information Figure A-41 shows a block diagram of the NI 6032E/6033E.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND AO EXT REF P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI PCI-MIO-16XE-10 (NI 6030E) Pinout Figure A-43 shows the PCI-MIO-16XE-10 (NI 6030E) device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND AO EXT REF P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI 6031E Pinout Figure A-44 shows the NI 6031E device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information AI GND AI GND AI 0 AI 8 AI 1 AI 9 AI 2 AI 10 AI 3 AI 11 AI 4 AI 12 AI 5 AI 13 AI 6 AI 14 AI 7 AI 15 AI SENSE AO 0 AO 1 AO EXT REF AO GND D GND P0.0 P0.4 P0.1 P0.5 P0.2 P0.6 P0.3 P0.
Appendix A Device-Specific Information For a detailed description of each signal, refer to the I/O Connector Signal Descriptions section of Chapter 1, DAQ System Overview. NI 6032E Pinout Figure A-45 shows the NI 6032E device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information AI 8 AI 1 AI GND AI 10 AI 3 AI GND AI 4 AI GND AI 13 AI 6 AI GND AI 15 NC NC NC P0.4 D GND P0.1 P0.
Appendix A Device-Specific Information NI 6033E Pinout Figure A-46 shows the NI 6033E device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information AI GND AI GND AI 0 AI 8 AI 1 AI 9 AI 2 AI 10 AI 3 AI 11 AI 4 AI 12 AI 5 AI 13 AI 6 AI 14 AI 7 AI 15 AI SENSE NC NC NC AO GND D GND P0.0 P0.4 P0.1 P0.5 P0.2 P0.6 P0.3 P0.
Appendix A Device-Specific Information For a detailed description of each signal, refer to the I/O Connector Signal Descriptions section of Chapter 1, DAQ System Overview. NI 6034E/6035E/6036E Family The NI 6034E/6035E/6036E are Plug-and-Play, multifunction AI, AO, DIO, and TIO devices.
Appendix A Device-Specific Information NI 6034E/6035E/6036E Block Diagrams Figure A-47 shows the block diagram of the NI PCI-6034E/6035E/6036E.
Appendix A Device-Specific Information Figure A-48 shows the block diagram of the DAQCard-6036E.
Appendix A Device-Specific Information AI 8 AI 1 AI GND AI 10 AI 3 AI GND AI 4 AI GND AI 13 AI 6 AI GND AI 15 NC NC NC P0.4 D GND P0.1 P0.
Appendix A Device-Specific Information NI 6035E Pinout Figure A-50 shows the NI 6035E device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND NC P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI 6036E Pinout Figure A-51 shows the NI 6036E device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information s AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND NC P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI 6040E Family NI PXI-6040E The NI PXI-6040E is a Plug-and-Play, multifunction AI, AO, DIO, and TIO device.
Appendix A Device-Specific Information Calibration DACs Voltage REF 3 Muxes 12-Bit Sampling A/D Converter NI-PGIA Gain Amplifier – Control Dither Circuitry Calibration Mux Configuration Memory AI Control I/O Connector 2 Trigger PFI/Trigger Trigger Analog Input Timing/Control DMA/ Interrupt Request Timing Counter/ Timing I/O DAQ - STC Bus Interface Digital I/O Analog Output Timing/Control RTSI Bus Interface Digital I/O (8) Address/ Data EEPROM IRQ DMA Analog Trigger Circuitry Tr
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND AO EXT REF P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information PCI-MIO-16E-4 The PCI-MIO-16E-4 is a Plug-and-Play, multifunction AI, AO, DIO, and TIO device for PCI bus computers.
Appendix A Device-Specific Information PCI-MIO-16E-4 Block Diagram Figure A-54 shows a block diagram of the PCI-MIO-16E-4.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND AO EXT REF P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI 6040E Family Specifications Refer to the NI 6040E Family Specifications for more detailed information on the devices. NI 6052E Family DAQPad-6052E The DAQPad-6052E is a Plug-and-Play, multifunction AI, AO, DIO, and TIO device.
Appendix A Device-Specific Information There are two versions of the NI DAQPad-6052E. Table A-5 illustrates the different I/O connectivity and form factors of each version. Table A-5. NI DAQPad-6052E Versions Model I/O Connector Form Factor DAQPad-6052E 68-pin SCSI-II male Full-size box (12.1 in. × 10 in. × 1.7 in.) Rack-mountable, stackable DAQPad-6052E BNC BNC and removable screw terminals Full-size box (12.1 in. × 10 in. × 1.7 in.) Rack-mountable, stackable E Series User Manual A-70 ni.
Appendix A Device-Specific Information DAQPad-6052E Block Diagram IEEE 1394 Figure A-56 shows a block diagram of the DAQPad-6052E.
Appendix A Device-Specific Information Differential Signals To connect differential signals, determine the type of signal source you are using: a floating signal source or a ground-referenced signal source. Refer to the Differential Connection Considerations and Connecting Analog Input Signals sections of Chapter 2, Analog Input, for more information on AI signals. To measure a floating signal source, move the switch to the FS position.
Appendix A Device-Specific Information Single-Ended Signals For each BNC connector that you use for two single-ended channels, set the source type switch to the GS position. This setting disconnects the built-in ground reference resistor from the negative terminal of the BNC connector, allowing the connector to be used as a single-ended channel, as shown in Figure A-59. AI x + 8 AI x GS FS 0.1 µF 5 kΩ AI GND Figure A-59.
Appendix A Device-Specific Information Refer to the Connecting Analog Output Signals section of Chapter 3, Analog Output, for more information. AO External Reference The AO EXT REF input controls the voltage range of analog output signals. Figure A-61 shows circuitry of the AO EXT REF on BNC DAQPads. AO EXT REF AI GND Figure A-61. AO EXT REF Refer to the Reference Selection section of Chapter 3, Analog Output, for more information.
Appendix A Device-Specific Information User <1..2> The User <1..2> signals connect directly from a screw terminal to a BNC. They allow you to use a BNC connector for a digital or timing I/O signal of your choice. The USER 1 BNC is internally connected to pin 21 and the USER 2 BNC is internally connected to pin 22 on the 30-pin I/O connector. Figure A-64 shows the connection of the User <1..2> BNCs. User 1 BNC Pin 21 User 2 BNC D GND 30-Pin I/O Connector D GND Pin 22 Figure A-64. User <1..
Appendix A Device-Specific Information Other Signals You can access other signals on BNC DAQPads through a 30-pin Combicon connector. To connect to one of these signals, use a small screwdriver to press down the orange spring release button at a terminal and insert a wire. Releasing the orange spring release button will lock the wire securely in place. You can remove the Combicon plugs to assist in connecting wires.
Appendix A Device-Specific Information DAQPad-6052E LED Patterns The DAQPad-6052E has an LED on its front panel. Refer to Table A-6 for descriptions of each LED state. Table A-6. DAQPad-6052E LEDs LED DAQPad-6052E State On The device is receiving power and is connected to an active 1394 port. Dim The device is receiving power but is not connected to an active 1394 port. Off No power is being provided to the device.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND AO EXT REF P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI DAQPad-6052E BNC Pinout Figure A-68 shows the NI DAQPad-6052E BNC device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information • Two 24-bit counter/timers for TIO • A 68-pin I/O connector Because the NI 6052E devices have no DIP switches, jumpers, or potentiometers, you can easily configure and calibrate them through software. NI PCI/PXI-6052E Block Diagram Figure A-69 shows a block diagram of the NI PCI/PXI-6052E.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND AO EXT REF P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI 6052E Family Specifications Refer to the NI 6052E Family Specifications for more detailed information on the devices. NI DAQCard-6062E The DAQCard-6062E is a multifunction AI, AO, DIO, and TIO DAQ device for computers equipped with Type II PCMCIA slots.
Appendix A Device-Specific Information DAQCard-6062E Block Diagram Figure A-71 shows a block diagram for the DAQCard-6062E.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND AO EXT REF P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI 6070E/6071E Family DAQPad-6070E The DAQPad-6070E is a Plug-and-Play, multifunction AI, AO, DIO, and TIO device. The DAQPad-6070E features the following: Note • 16 AI channels (eight differential) with 12-bit resolution • Two AO channels with 12-bit resolution • Eight lines of TTL-compatible DIO • Two 24-bit counter/timers for TIO • A 68-pin I/O connector The BNC version of the DAQPad-6070E has a 30-pin I/O connector.
Appendix A Device-Specific Information Table A-7. NI DAQPad-6070E Versions DAQ Device I/O Connector Form Factor DAQPad-6070E 68-pin SCSI-II male Full-size box (12.1 in. × 10 in. × 1.7 in.) Rack-mountable, stackable DAQPad-6070E BNC BNC and removable screw terminals Full-size box (12.1 in. × 10 in. × 1.7 in.) Rack-mountable, stackable E Series User Manual A-86 ni.
Appendix A Device-Specific Information DAQPad-6070E Block Diagram IEEE 1394 Figure A-73 shows the block diagram of the DAQPad-6070E.
Appendix A Device-Specific Information Differential Signals To connect differential signals, determine the type of signal source you are using: a floating signal source or a ground-referenced signal source. Refer to the Differential Connection Considerations and Connecting Analog Input Signals sections of Chapter 2, Analog Input, for more information. To measure a floating signal source, move the switch to the FS position. To measure a ground-referenced signal source, move the switch to the GS position.
Appendix A Device-Specific Information Single-Ended Signals For each BNC connector that you use for two single-ended channels, set the source type switch to the GS position. This setting disconnects the built-in ground reference resistor from the negative terminal of the BNC connector, allowing the connector to be used as a single-ended channel, as shown in Figure A-76. AI x + 8 AI x GS FS 0.1 µF 5 kΩ AI GND Figure A-76.
Appendix A Device-Specific Information Refer to the Connecting Analog Output Signals section of Chapter 3, Analog Output, for more information. AO External Reference The AO EXT REF input controls the voltage range of analog output signals. Figure A-78 shows circuitry of the AO EXT REF on BNC DAQPads. AO EXT REF AI GND Figure A-78. AO EXT REF Refer to the Reference Selection section of Chapter 3, Analog Output, for more information.
Appendix A Device-Specific Information User <1..2> The User <1..2> signals connect directly from a screw terminal to a BNC. They allow you to use a BNC connector for a digital or timing I/O signal of your choice. The USER 1 BNC is internally connected to pin 21 and the USER 2 BNC is internally connected to pin 22 on the 30-pin I/O connector. Figure A-81 shows the connection of the User <1..2> BNCs. User 1 BNC Pin 21 User 2 BNC D GND 30-Pin I/O Connector Pin 22 D GND Figure A-81. User <1..
Appendix A Device-Specific Information You can remove the Combicon plugs to assist in connecting wires. Loosening the screws on either side of the two Combicon plugs allows you to detach the Combicon plugs from the BNC DAQPad device, as shown in Figure A-83. Figure A-83. Removing the BNC Combicon E Series User Manual A-92 ni.
Appendix A Device-Specific Information DAQPad-6070E LED Patterns The DAQPad-6070E has an LED on its front panel. Refer to Table A-8 for descriptions of each LED state. Table A-8. DAQPad-6070E LEDs LED DAQPad-6070E State On The device is receiving power and is connected to an active 1394 port. Dim The device is receiving power but is not connected to an active 1394 port. Off No power is being provided to the device.
Appendix A Device-Specific Information PFI 9 PFI 8 PFI 7 PFI 6 PFI 5 PFI 4 PFI 3 PFI 2 PFI 1 D GND USER 2 FREQ OUT +5 V +5 V D GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 CTR 1 OUT D GND USER 1 AI HOLD COMP EXT STROBE AI SENSE AI GND Figure A-84. NI DAQPad-6070E BNC Pinout For a detailed description of each signal, refer to the I/O Connector Signal Descriptions section of Chapter 1, DAQ System Overview.
Appendix A Device-Specific Information Because the NI 6070E/6071E have no DIP switches, jumpers, or potentiometers, you can easily configure and calibrate them through software. NI 6070E/6071E Block Diagram Figure A-85 shows a block diagram of the NI PCI/PXI-6070E and NI PCI-6071E.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND AO EXT REF P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI PCI-6071E Pinout Figure A-87 shows the NI 6071E device pinout. Note Some hardware accessories may not yet reflect the NI-DAQmx terminal names. If you are using an E Series device in Traditional NI-DAQ (Legacy), refer to Table 1-5, Terminal Name Equivalents, for the Traditional NI-DAQ (Legacy) signal names.
Appendix A Device-Specific Information AI GND AI GND AI 0 AI 8 AI 1 AI 9 AI 2 AI 10 AI 3 AI 11 AI 4 AI 12 AI 5 AI 13 AI 6 AI 14 AI 7 AI 15 AI SENSE AO 0 AO 1 AO EXT REF AO GND D GND P0.0 P0.4 P0.1 P0.5 P0.2 P0.6 P0.3 P0.
Appendix A Device-Specific Information For a detailed description of each signal, refer to the I/O Connector Signal Descriptions section of Chapter 1, DAQ System Overview. PCI-MIO-16E-1 The PCI-MIO-16E-1 is a Plug-and-Play, multifunction AI, AO, DIO, and TIO device for PCI bus computers.
Appendix A Device-Specific Information PCI-MIO-16E-1 Block Diagram Figure A-88 shows a block diagram of the PCI-MIO-16E-1.
Appendix A Device-Specific Information AI 8 34 68 AI 0 AI 1 33 67 AI GND AI GND 32 66 AI 9 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI GND 29 63 AI 11 AI 4 28 62 AI SENSE AI GND 27 61 AI 12 AI 13 26 60 AI 5 AI 6 25 59 AI GND AI GND 24 58 AI 14 AI 15 23 57 AI 7 AO 0 22 56 AI GND AO 1 21 55 AO GND AO EXT REF P0.4 20 54 19 53 AO GND D GND D GND 18 52 P0.0 P0.1 17 51 P0.5 P0.6 16 50 D GND D GND 15 49 P0.2 +5 V 14 48 P0.7 D GND 13 47 P0.
Appendix A Device-Specific Information NI 6070E/6071E Specifications Refer to the NI 6070E/6071E Family Specifications for more detailed information on the devices. E Series User Manual A-102 ni.
B I/O Connector Pinouts Table corresponds each E Series device to the associated I/O connector pinouts for that device and compatible accessories. Table B-1. E Series I/O Connector Pinouts E Series Device Typical Cable Accessory SH6868EP Refer to Figure A-4. SH6850 Refer to Figure B-4. SH6868EP Refer to Figure A-5. SH6850 Refer to Figure B-4. NI DAQPad-6015 — — NI DAQPad-6015 BNC — — NI DAQPad-6015 Mass Termination — — NI DAQPad-6016 — — SH6868EP Refer to Figure A-33.
Appendix B I/O Connector Pinouts Table B-1. E Series I/O Connector Pinouts (Continued) E Series Device NI 6030E NI 6031E NI 6032E NI 6033E NI 6034E NI 6035E NI 6036E NI 6040E NI 6052E NI DAQPad-6052E BNC NI 6062E NI PCI/PXI-6070E NI DAQPad-6070E BNC E Series User Manual Typical Cable Accessory SH6868EP Refer to Figure A-42. SH6850 Refer to Figure B-4. SH1006868 Refer to Figure B-1. SH100100 Refer to Figure A-44. R1005050 Refer to Figure B-3. SH6868EP Refer to Figure A-45.
Appendix B I/O Connector Pinouts Table B-1. E Series I/O Connector Pinouts (Continued) E Series Device Typical Cable Accessory SH1006868 Refer to Figure B-1. SH100100 Refer to Figure A-87. R1005050 Refer to Figure B-3. NI PCI-MIO-16E-1 (NI 6070E) SH6868EP Refer to Figure A-88. SH6850 Refer to Figure B-4. NI PCI-MIO-16E-4 (NI 6040E) SH6868EP Refer to Figure A-55. SH6850 Refer to Figure B-4. NI PCI-MIO-16XE-10 (NI 6030E) SH6868EP Refer to Figure A-43. SH6850 Refer to Figure B-4.
Appendix B I/O Connector Pinouts MIO-16 Connector Extended I/O Connector AI 8 34 68 AI 0 AI 24 34 68 AI 16 AI 1 33 67 AI GND AI 17 33 67 AI 25 AI GND 32 66 AI 9 AI 18 32 66 AI 26 AI 10 31 65 AI 2 AI 3 30 64 AI GND AI 27 31 65 AI 19 AI GND 29 63 AI 11 AI 20 30 64 AI 28 AI 4 28 62 AI SENSE AI 21 29 63 AI 29 AI GND 27 61 AI 12 AI 30 28 62 AI 22 AI 13 26 60 AI 5 AI 23 27 61 AI 31 AI GND AI 32 26 60 AI 40 AI 14 AI 41 25 59 AI 33 AI 7 AI 34 24 58 A
Appendix B MIO-16 Connector I/O Connector Pinouts Extended I/O Connector AI 8 34 68 AI 0 D GND 34 68 P3.7 AI 1 33 67 AI GND P3.6 33 67 D GND AI GND 32 66 AI 9 P3.5 32 66 D GND AI 10 31 65 AI 2 D GND 31 65 P3.4 AI 3 30 64 AI GND P3.3 30 64 D GND AI GND 29 63 AI 11 P3.2 29 63 D GND AI 4 28 62 AI SENSE D GND 28 62 P3.1 AI GND 27 61 AI 12 P3.0 27 61 D GND AI 13 26 60 AI 5 P2.7 26 60 D GND AI 6 25 59 AI GND D GND 25 59 P2.6 AI GND 24 58 AI 14 P2.
Appendix B I/O Connector Pinouts 100-50-50-Pin 100-50-50-Pin Extended AI I/O Connector Pinout When you use the NI 6025E with an R1005050 cable assembly, the signals appear on two 50-pin connectors. Figure B-3 shows the pinouts of the 50-pin connectors. E Series User Manual B-6 ni.
Appendix B I/O Connector Pinouts 100-50-50-Pin Extended DIO I/O Connector Pinout When you use the NI 6025E with an R1005050 cable assembly, the signals appear on two 50-pin connectors. Figure B-3 shows the pinouts of the 50-pin connectors. Positions 1–50 Connector 1 Positions 51–100 Connector AI GND AI 8 AI 9 AI 10 AI 11 AI 12 AI 13 AI 14 AI 15 AO 01 AO EXT REF1 D GND P0.4 P0.5 P0.6 P0.7 +5 V AI HOLD COMP PFI 0/AI START TRIG PFI 2/AI CONV CLK PFI 4/CTR 1 GATE P3.7 1 2 D GND P3.6 3 4 D GND P3.
Appendix B I/O Connector Pinouts 50-Pin MIO I/O Connector Pinout Figure B-4 shows the 50-pin I/O connector that is available when you use the R6850 or SH6850 cable assemblies with 68-pin E Series devices. AI GND AI 0 1 2 3 4 AI 1 AI 2 5 6 7 8 AI 3 AI 4 AI 5 AI 6 AI 7 AI SENSE AO 11 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AO GND1 23 24 P0.0 P0.1 25 26 P0.2 P0.
C Troubleshooting This appendix contains some common questions about E Series devices. If your questions are not answered here, refer to the National Instruments KnowledgeBase at ni.com. It contains thousands of documents that answer frequently asked questions about NI products. Analog Input I am seeing crosstalk or ghost voltages when sampling multiple channels.
Appendix C Troubleshooting reference the signal to the same ground level as the device reference. There are various methods of achieving this reference while maintaining a high common-mode Rejection Ratio (CMRR). These methods are outlined in the Connecting Analog Input Signals section of Chapter 2, Analog Input. AI GND is an AI common signal that routes directly to the ground connection point on the devices. You can use this signal if you need a general analog ground connection point to the device.
Appendix C Troubleshooting Register-Level Programming Information Caution NI is not liable for any damage or injury that results from register-level programming the E Series devices. Refer to ni.com/manuals for register-level programming manuals that are available for E Series devices. The National Instruments Measurement Hardware DDK provides development tools and a register-level programming interface for NI data acquisition hardware.
Technical Support and Professional Services D Visit the following sections of the National Instruments Web site at ni.com for technical support and professional services: • Support—Online technical support resources at ni.
Appendix D Technical Support and Professional Services • Calibration Certificate—If your product supports calibration, you can obtain the calibration certificate for your product at ni.com/calibration. If you searched ni.com and could not find the answers you need, contact your local office or NI corporate headquarters. Phone numbers for our worldwide offices are listed at the front of this manual. You also can visit the Worldwide Offices section of ni.
Glossary Symbol Prefix Value p pico 10 –12 n nano 10 –9 μ micro 10 – 6 m milli 10 –3 k kilo 10 3 M mega 10 6 G giga 10 9 T tera 10 12 Symbols % Percent. + Positive of, or plus. / Per. ° Degree. Ω Ohm. A A Amperes—the unit of electric current. AC Alternating current. ADE Application development environment. AI Analog input. Analog input channel signal. AI GND Analog input ground signal.
Glossary AI SENSE Analog input sense signal. AO Analog output. AO 0 Analog channel 0 output signal. AO 1 Analog channel 1 output signal. AO GND Analog output ground signal. B bipolar A signal range that includes both positive and negative values (for example, −5 to +5 V). C channel Physical—a terminal or pin at which you can measure or generate an analog or digital signal.
Glossary CMOS Complementary metal-oxide semiconductor. counter/timer A circuit that counts external pulses or clock pulses (timing). D DAC Digital-to-analog converter—an electronic device, often an integrated circuit, that converts a digital number into a corresponding analog voltage or current. DAQ See data acquisition (DAQ). DAQ device A device that acquires or generates data and can contain multiple channels and conversion devices.
Glossary H hysteresis Lag between making a change and the effect of the change. I interchannel delay Amount of time that passes between sampling consecutive channels. The interchannel delay must be short enough to allow sampling of all the channels in the channel list, within the scan interval. The greater the interchannel delay, the more time the PGIA is allowed to settle before the next channel is sampled. The interchannel delay is regulated by the AI CONV signal.
Glossary NI-DAQmx The latest NI-DAQ driver with new VIs, functions, and development tools for controlling measurement devices. The advantages of NI-DAQmx over earlier versions of NI-DAQ include the DAQ Assistant for configuring channels and measurement tasks for your device for use in LabVIEW, LabWindows/CVI, and Measurement Studio; increased performance such as faster single-point analog I/O; and a simpler API for creating DAQ applications using fewer functions and VIs than earlier versions of NI-DAQ.
Glossary RTSI Real-Time System Integration—the National Instruments timing bus that connects DAQ devices directly, by means of connectors on top of the devices, for precise synchronization of functions. S s Seconds. S Samples. S/s Samples per second—Used to express the rate at which a digitizer or D/A converter or DAQ device samples an analog signal. scan interval Controls how often a scan is initialized; is regulated by the AI Sample Clock signal. scan rate Reciprocal of the scan interval.
Glossary tout Output delay time. Traditional NI-DAQ (Legacy) An upgrade to the earlier version of NI-DAQ. Traditional NI-DAQ (Legacy) has the same VIs and functions and works the same way as NI-DAQ 6.9.x. You can use both Traditional NI-DAQ (Legacy) and NI-DAQmx on the same computer, which is not possible with NI-DAQ 6.9.x. transducer See sensor. tsc Source clock period. tsp Source pulse width.
Index Numerics analog trigger types, 10-4 and BNC, A-13, A-26, A-71, A-87 ANSI C documentation, xix AO applications, 3-15 AO data generation, 3-4 AO External Reference, A-29, A-74, A-90 AO External Reference on BNC DAQPads, A-29, A-74, A-90 AO Pause Trigger, 3-7, 3-10 AO Sample Clock, 3-11 AO Sample Clock Timebase, 3-13 AO Start Trigger, 3-6, 3-9 100-50-50-pin extended AI, B-6 100-68-68-pin extended AI, B-3 100-68-68-pin extended DIO, B-3 50-pin MIO connector, B-8 A A/D conversion, 2-1 A/D converter, 2-1
Index C D cabling, 2-11 calibration certificate (NI resources), D-2 calibration circuitry, 1-4 circuitry, 2-1, 3-1 clocks, 8-4 Combicon connector, A-17, A-31, A-76, A-91 CompactPCI, 9-1 configuration, 4-2 configuring AI modes in, 2-29, 2-31 configuring PFIs, 6-1 connecting, 4-9, 7-4 Connecting Analog Input Signals, 2-20 connecting signals, 2-20, 3-8, A-13, A-26, A-71 connecting signals on BNC DAQPads, A-13, A-26, A-71 connections, 8-1 considerations, 2-22, 2-26 counter, 5-1, 5-2 Counter 0 Gate, 5-4 Count
Index G dither, 2-8, A-2, A-44 documentation .
Index N NI 6036E, A-61, A-62 pinout, A-62 NI 6040E, A-64 family, A-63, A-69 NI 6040E (NI PCI-MIO-16E-4), A-67, A-68 NI 6052E, A-77, A-78, A-79, A-80, A-81 family, A-69, A-82 pinout, A-78, A-81 NI 6062E, A-82, A-83 family, A-83 pinout, A-84 NI 6070E, A-95, A-96 pinout, A-96 NI 6070E (NI PCI-MIO-16E-1), A-100, A-101 NI 6070E/6071E, A-94, A-95 family, A-85 NI 6071E, A-97, A-98 pinout, A-98 NI DAQCard-6062E, A-82, A-83 NI DAQPad-6015, A-21 Mass Termination, A-22 pinout, A-23 pinout, A-21 NI DAQPad-6015 BNC, A
Index PCI-6071E, A-85, A-94 PCI-MIO-16E-1 (NI 6070E/6071E Family) A-99 PCI-MIO-16E-4, A-66 PCI-MIO-16E-4 (NI 6040E Family), A-66 PCI-MIO-16XE-10 (NI 6030E/6031E/ 6032E/6033E Family), A-43 PCI-MIO-16XE-50, A-2 PCI-MIO-16XE-50 (NI 6011E), A-1 PFI, 6-1 PFI 0/AI START TRIG, 10-2 PFI 0/AI Start Trigger, A-15, A-29, A-74, A-90 PFI 0/AI Start Trigger on BNC DAQPads, A-15, A-29, A-74, A-90 PFI and DIO lines, 4-9 PFI connections, 6-1 pinout 100-50-50-pin extended I/O connector, B-7 100-68-68-pin extended AI I/O con
Index RTSI, 8-1 bus, 8-1 clocks, 8-4 triggers, 8-1 NI DAQPad-6015 BNC, A-22 NI DAQPad-6015 Mass Termination, A-23 NI DAQPad-6016, A-24 NI DAQPad-6020E, A-33 NI DAQPad-6020E BNC, A-34 NI DAQPad-6052E, A-78 NI DAQPad-6052E BNC, A-79 NI DAQPad-6070E BNC, A-94 NI PCI/PXI-6052E, A-81 NI PCI/PXI-6070E, A-96 NI PCI-6071E, A-98 NI PCI-MIO-16E-1 (NI 6070E), A-101 NI PCI-MIO-16E-4 (NI 6040E), A-68 NI PCI-MIO-16XE-10 (NI 6030E), A-48 polarity selection, 3-3 port 3 signal assignments, 4-2 power-on state, 4-3 programm
Index W training, xx training and certification (NI resources), D-1 triggering, 2-14, 3-5, 10-1 triggers, 8-1 troubleshooting, C-1 NI resources, D-1 Types of Signal Sources, 2-22 Web resources, D-1 wiring, 2-28 with a digital source, 10-1 with an analog source, 10-2 U User on BNC DAQPads, A-16, A-30, A-75, A-91 User <1..
