User manual

Chapter 3 Software Overview
NI-DAQ User Manual for PC Compatibles 3-80 ni.com
Counter operation starts and stops relative to the selected timebase.
When a counter is configured for no gating, the counter starts at the first
timebase/source edge (rising or falling, depending on the selection) after
the software configures the counter. When a counter is configured for
gating modes, gate signals take effect at the next timebase/source edge.
For example, if a counter is configured to count rising edges and to use
the falling edge gating mode, the counter starts counting on the next rising
edge after it receives a high-to-low edge on its GATE input. Thus, some
time is spent synchronizing the GATE input with the timebase/source. This
synchronization time creates a time lapse uncertainty from 0 to 1 timebase
period between the signal application at the GATE input and the start of the
counter operation.
The counter generates timing signals at its OUT output. If the counter is not
operating, you can set its output to one of three states—high-impedance
state, low-logic state, or high-logic state.
The counters generate two types of output signals during counter
operation—TC pulse output and TC toggled output. A counter reaches TC
when it counts up to 65,535 or down to 0 and rolls over. In many counter
applications, the counter reloads from an internal register when it reaches
TC. In TC pulse output mode, the counter generates a pulse during the cycle
in which it reaches TC. In TC toggled output mode, the counter output
changes state on the next source edge after reaching TC. In addition, you
can configure the counters for positive logic output or negative (inverted)
logic output. Figure 3-27 shows examples of the four types of output
signals generated.