User manual

Chapter 3 Software Overview

operation. In addition, the data acquisition functions

DAQ_Start

and

Lab_ISCAN_Start

cannot use counter B0 if the total sample interval for

data acquisition is also greater than 65,535 µs, unless the timebase required

for data acquisition is the same as the timebase counter B0 produces for

waveform generation. If data acquisition is not in progress, counter B0 is

available for waveform generation if

ICTR_Setup

has not been called

on counter B0 since startup, or an

CTR_Reset

call has been made on

counter B0. If data acquisition is in progress and is using counter B0

to produce the sample timebase, counter B0 is available for waveform

generation only if this timebase is the same as required by the Waveform

Generation functions to produce the total update interval. In this case,

counter B0 produces the same timebase for data acquisition and waveform

generation.

On the AT-AO-6/10, counter 0 produces the total update interval for

group 1 waveform generation, and counter 1 produces the total update

interval for group 2 waveform generation. However, if the total update

interval is greater than 65,535 µs for either group 1 or 2, counter 2 is used

by counter 0 (group 1) or counter 1 (group 2) to produce the total update

interval. If either group is using counter 2 to produce the sample timebase,

counter 2 is available to the other group only if the timebase is the same

as the timebase required by the Waveform Generation functions to produce

the total update interval. In this case, counter 2 produces the same timebase

for both waveform generation groups.

FIFO Lag Effect on the MIO, E Series, AT-AO-6/10,

NI 4451 for PCI, NI 4551 for PCI, 622X, and 671X Devices

Group 1 analog output channels use an onboard FIFO to output data values

to the DACs. NI-DAQ continuously writes values to the FIFO as long as

the FIFO is not full. NI-DAQ transfers data values from the FIFO to the

DACs at regular intervals using an onboard or external clock. You see a lag

effect for group 1 channels because of the FIFO buffering. That is, a value

written to the FIFO is not output to the DAC until all of the data values

currently in the FIFO have been output to the DACs. This time lag is

dependent upon the update rate (specified in

WFM_ClockRate

). Refer to

your device user manual for a more detailed discussion of the

onboard FIFO.