Datasheet

DTM64343A
4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM
Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 Page 9
CAS Latencies Supported, Most Significant Byte
Bit 0. CL = 12 -
Bit 1. CL = 13 -
Bit 2. CL =14 -
Bit 3. CL = 15 -
Bit 4. CL = 16 -
Bit 5. CL = 17 -
Bit 6. CL = 18 -
15
Bit 7. Reserved.
00
16 Minimum CAS Latency Time (tAAmin) 13.125ns 69
17 Minimum Write Recovery Time (tWRmin) 15.0ns 78
18 Minimum RAS# to CAS# Delay Time (tRCDmin) 13.125ns 69
19 Minimum Row Active to Row Active Delay Time (tRRDmin) 6.0ns 30
20 Minimum Row Precharge Delay Time (tRPmin) 13.125ns 69
Upper Nibbles for tRAS and tRC
Bit 3 ~ Bit 0. tRAS Most Significant Nibble - 1
21
Bit 7 ~ Bit 4. tRC Most Significant Nibble - 1
11
22
Minimum Active to Precharge Delay Time (tRASmin), Least
Significant Byte
36.0ns 20
23
Minimum Active to Active/Refresh Delay Time (tRCmin), Least
Significant Byte
49.125ns 89
24
Minimum Refresh Recovery Delay Time (tRFCmin), Least
Significant Byte
160.0ns 00
25
Minimum Refresh Recovery Delay Time (tRFCmin), Most
Significant Byte.
160.0ns 05
26 Minimum Internal Write to Read Command Delay Time (tWTRmin) 7.5ns 3C
27
Minimum Internal Read to Precharge Command Delay Time
(tRTPmin)
7.5ns 3C
Upper Nibble for tFAW
Bit 3 ~ Bit 0. tFAW Most Significant Nibble - 0
28
Bit 7 ~ Bit 4. Reserved - 0
00
29
Minimum Four Activate Window Delay Time (tFAWmin), Least
Significant Byte
30ns F0
SDRAM Optional Features
Bit 0. RZQ / 6 - X
Bit 1. RZQ / 7 - X
Bit 6 ~ Bit 2. Reserved -
30
Bit 7. DLL-Off Mode Support
83
SDRAM Drivers Supported
Extended Temperature Range - X
Extended Temperature Refresh Rate -
Auto Self Refresh (ASR) -
On-die Thermal Sensor (ODTS) Readout -
Reserved -
Reserved -
Reserved -
31
Reserved -
01