Datasheet
DTM65521A
2 GB - 256Mx72, 240-Pin FB-DIMM
Document 06054, Revision A, 1-Aug-08, Dataram Corporation © 2008 Page 11
DRAM AC Characteristics (AC operating conditions unless otherwise noted)
Parameter Symbol
Min
Value
Max
Value
Unit Note
Row Cycle Time
t
RC
60 - ns
Auto Refresh Row Cycle Time
t
RFC
127.5 - ns
Row Active Time
t
RAS
45 70K ns
Row Address to Column Address Delay
t
RCD
15 - ns
Row Active to row Active Delay
t
RRD
7.5 - ns
Column Address to Column Address Delay
t
CCD
2 - CLK
Row Precharge time
t
RP
15 - ns
Write Recovery Time
t
WR
15 - ns
Auto Precharge Write Recovery + Precharge Time
t
DAL
(t
WR
/ t
CK
)
+ (t
RP
/
t
CK
)
- ns
System Clock Cycle Time
t
CK
3000 8000 ps
Clock High Level Width
t
CH
0.48 0.52 CLK
Clock Low Level Width
t
CL
0.48 0.52 CLK
DQ output access time from CK & /CK
t
AC
-0.450 +0.450 ns
DQS-Out edge to Clock Edge skew
t
DQSCK
-0.400 +0.400 ns
DQS-Out edge to Data-out edge skew
t
DQSQ
- 0.240 ns
Data-Out hold time from DQS
t
QH
t
HP
- t
QHS
- ns 1
Data hold skew factor
t
QHS
- 0.340 ns 1
Clock Half Period
t
HP
min (t
CL
, t
CH
) - ns 1
Input Setup Time (fast slew rate)
t
IS
0.200 - ns 2,3,5,6
Input Hold Time (fast slew rate)
t
IH
0.275 - ns 2,3,5,6
Input Pulse Width
t
IPW
0.6 - CLK 6
Write DQS High Level Width
t
DQSH
0.35 - CLK
Write DQS Low Level Width
t
DQSL
0.35 - CLK
CLK to First Rising edge to DQS-In
t
DQSS
-0.25 +0.25 CLK
Data-In Setup Time to DQS-In (DQ & DM)
t
DS
0.100 - ns 7
Data-In Hold Time to DQS-In (DQ & DM)
t
DH
0.175 - ns 7
NOTES:
1. This calculation accounts for t
DQSQ
(max), the pulse width distortion of on-chip and jitter.
2. Data sampled at the rising edges of the clock: A0~A13, BA0~BA2, CKE, /S[1:0], /RAS, /CAS, /WE
3. For command/address input slew rate > = 1.0V/ns
4. For command/address input slew rate > = 0.5V/ns and <1.0V/ns
5. CK,/CK slew rates are > = 1.0V/ns
6. These Parameters guarantee device timing, but they are not necessarily tested on each device, and they may be
guaranteed by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes (DQS)