Datasheet

DTM65536B
2 GB - 240-Pin DDR2 Low Power FB-DIMM
Document 06038, Revision A, 29-Sep-09, Dataram Corporation © 2010 Page 14
SDRAM Write Recovery Times Supported
Bit 3 ~ Bit 0. Minimum WR (clocks) - 2
15
Bit 7 ~ Bit 4. WR Range (clocks) - 4
0x42
16
SDRAM Write Recovery Time (tWR).
15.0ns 0x3C
SDRAM Write Latencies Supported
Bit 3 ~ Bit 0. Minimum WL (clocks) - 2
17
Bit 7 ~ Bit 4. WL Range (clocks) - 4
0x42
SDRAM Additive Latencies Supported.
Bit 3 ~ Bit 0. Minimum AL (clocks)- 0
18
Bit 7 ~ Bit 4. AL Range (clocks) - 4
0x40
19 SDRAM Minimum RAS to CAS Delay (tRCD). 15.0ns 0x3C
20 SDRAM Minimum Row Active to Row Active Delay (tRRD). 7.5ns 0x1E
21 SDRAM Minimum Row Precharge Time (tRP). 15.0ns 0x3C
SDRAM Upper Nibbles for tRAS and tRC.
Bit 3 ~ Bit 0. tRAS Most Significant Nibble -
22
Bit 7 ~ Bit 4. tRC Most Significant Nibble -
0x00
23 SDRAM Minimum Active to Precharge Time (tRAS). 45.0ns 0xB4
24 SDRAM Minimum Active to Active/Refresh Time (tRC).
60.0ns
0xF0
25
SDRAM Minimum Refresh Recovery Time Delay (tRFC),
(LSB).
127.5ns 0xFE
26
SDRAM Minimum Refresh Recovery Time Delay (tRFC),
(MSB).
127.5ns 0x01
27
SDRAM Minimum Internal Write to Read Command Delay
(tWTR).
7.5ns 0x1E
28
SDRAM Minimum Internal Read to Precharge Command
Delay (tRTP).
7.5ns 0x1E
SDRAM Burst Lengths Supported
Bit 0. BL = 4 - X
Bit 1. BL = 8 - X
Bit 6 ~ Bit 2.TBD
29
Bit 7. Burst Chop -
0x03
SDRAM Terminations Supported.
Bit 0. 150 ohms ODT - X
Bit 1. 75 ohms ODT - X
Bit 2. 50 ohms ODT - X
30
Bit 6 ~ Bit 3.TBD
0x07
SDRAM Drivers Supported.
Bit 0. Weak Driver - X
31
Bit 7 ~ Bit 1. TBD
0x01
SDRAM Average Refresh Interval (tREFI) / Double Refresh mode bit / High
Temperature self-refresh rate support indication.
32
Bit 0 ~ Bit 3. Average Refresh Interval (tREFI) uS - 7.8
0xC2