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DTM68104A

8GB - 288-Pin 2Rx8 Unbuffered Non-ECC DDR4 DIMM

Features Identification

288-pin JEDEC-compliant DIMM, 133.35 mm wide by 31.25 mm

high

DTM68104A 1Gx64

8G 2Rx8 PC4-2133P-UB0-10

Performance range

Clock / Module Speed / CL-t

RCD

-t

1067 MHz / PC4-2133 / 16-16-16

1067 MHz / PC4-2133 / 15-15-15

933 MHz / PC4-1866 / 14-14-14

933 MHz / PC4-1866 / 13-13-13

800 MHz / PC4-1600 / 12-12-12

800 MHz / PC4-1600 / 11-11-11

667 MHz / PC4-1600 / 10-10-10

667 MHz / PC4-1600 / 9-9-9

Description

DTM68104A is an unbuffered 1Gx64

memory module, which conforms to

JEDEC's DDR4-2133, PC4-2133 standard.

The assembly is Dual-Rank. Each rank is

comprised of eight Samsung 512Mx8

DDR4-2133 SDRAMs. One 4K-bit

EEPROM is used for Serial Presence

Detect.

Both output driver strength and input

termination impedance are programmable

to maintain signal integrity on the I/O

signals in a Fly-by topology. A thermal

sensor accurately monitors the DIMM

module and can prevent exceeding the

maximum operating temperature of 95C.

Operating Voltage: VDD/VDDQ = 1.2V (1.14V to 1.26V)

VPP = 2.5V (2.375V to 2.75V)

VDDSPD = 2.25V to 2.75V

I/O Type: 1.2 V signaling

On-board I

C temperature sensor with integrated Serial

Presence-Detect (SPD) EEPROM

Data Transfer Rate: 17.0 Gigabytes/sec

Data Bursts: 8 and burst chop 4 mode

ZQ Calibration for Output Driver and On-Die Termination (ODT)

Programmable ODT / Dynamic ODT during Writes

Programmable CAS Latency: 9, 10, 11, 12, 13, 14, 15 and 16

Bi-directional Differential Data Strobe signals

Per DRAM Addressability is supported

Write CRC is supported at all speed grades

DBI (Data Bus Inversion) is supported(x8 only)

CA parity (Command/Address Parity) mode is supported

Supports ECC error correction and detection

16 internal banks

SDRAM Addressing (Row/Col/BG/BA): 15/10/2/2

Fully RoHS Compliant



Summary of content (9 pages)

PAGE 1
DTM68104A 8GB - 288-Pin 2Rx8 Unbuffered Non-ECC DDR4 DIMM Features Identification 288-pin JEDEC-compliant DIMM, 133.35 mm wide by 31.25 mm high Operating Voltage: VDD/VDDQ = 1.2V (1.14V to 1.26V) DTM68104A 1Gx64 8G 2Rx8 PC4-2133P-UB0-10 VPP = 2.5V (2.375V to 2.75V) VDDSPD = 2.25V to 2.75V I/O Type: 1.2 V signaling On-board I2C temperature sensor with integrated Serial Presence-Detect (SPD) EEPROM Data Transfer Rate: 17.
PAGE 2
DTM68104A 8GB - 288-Pin 2Rx8 Unbuffered Non-ECC DDR4 DIMM Speed Bin Table Speed Bin DDR4‐2133P DDR4‐2133R CL‐nRCD‐nRP 15‐15‐15 16‐16‐16 Parameter Symbol Unit min max min max 14.0614 (13.50)5,12 18.00 15.00 18.00 ns TBD TBD TBD TBD ns Internal read command to first data tAA Internal read command to first data with read DBI enabled tAA_DBI ACT to internal read or write delay time tRCD 14.06 (13.50)5,12 ‐ 15.00 ‐ ns PRE command period tRP 14.06 (13.50)5,12 ‐ 15.
PAGE 3
DTM68104A 8GB - 288-Pin 2Rx8 Unbuffered Non-ECC DDR4 DIMM Speed Bin Table Notes: Absolute Specification ‐ VDDQ = VDD = 1.20V +/‐ 0.06 V ‐ VPP = 2.5V +0.25/‐0.125 V ‐ The values defined with above‐mentioned table are DLL ON case. ‐ DDR4‐1600, 1866, 2133 and 2400 Speed Bin Tables are valid only when Geardown Mode is disabled. 1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements.
PAGE 4
DTM68104A 8GB - 288-Pin 2Rx8 Unbuffered Non-ECC DDR4 DIMM Pin Configuration Front Side 1 12V,NC 37 VSS 73 Back Side VDD 109 VSS 145 12V,NC 181 DQ29 217 VDD 253 DQ41 2 VSS 38 DQ24 74 CK0_t 110 DM5_n, DBI5_n 146 VREFCA 182 VSS 218 CK1_t 254 VSS 3 DQ4 39 VSS 75 CK0_c 111 NC 147 VSS 183 DQ25 219 CK1_c 255 DQS5_c 4 VSS 40 DM3_n, DBI3_n 76 VDD 112 VSS 148 DQ5 184 VSS 220 VDD 256 DQS5_t 5 DQ0 41 NC 77 VTT 113 DQ46 149 VSS 185 DQS3_c 221 V
PAGE 5
DTM68104A 8GB - 288-Pin 2Rx8 Unbuffered Non-ECC DDR4 DIMM PIN DESCRIPTION Name Function CB[7:0] * Data Check Bits DQ[63:0] Data Bits DM[7:0]_n, DBI[7:0]_n Input Data Mask and Data Bus Inversion DQS[7:0]_t, DQS[7:0]_c Differential Data Strobes CK_t[1:0], CK_c[1:0] Differential Clock Inputs CKE[1:0] Clock Enables CAS_n / A15 Multiplexed: Column Address Strobe or Address 15 RAS_n / A16 Multiplexed: Row Address Strobe or Address 16 CS[1:0]_n, CS[3:2]_n* Chip Selects ACT_n Activate Command I
PAGE 6
DTM68104A 8GB - 288-Pin 2Rx8 Unbuffered Non-ECC DDR4 DIMM Side View 3.98mm (max) 1.4 +/- .1mm (max) Notes: 1. Tolerances on all dimensions except where otherwise indicated are ±.13. Reference JEDEC standard MO-309C. 2.
PAGE 7
DTM68104A 8GB - 288-Pin 2Rx8 Unbuffered Non-ECC DDR4 DIMM Functional Diagram (Rank 0) Notes: 1: Unless otherwise noted, resistor values are 15Ω ± 5%. 2: ZQ resistors are 240Ω ± 1%. For all other resistor values refer to the appropriate wiring diagram.
PAGE 8
DTM68104A 8GB - 288-Pin 2Rx8 Unbuffered Non-ECC DDR4 DIMM Functional Diagram (Rank 1) Notes: 1: Unless otherwise noted, resistor values are 15Ω ± 5%. 2: ZQ resistors are 240Ω ± 1%. For all other resistor values refer to the appropriate wiring diagram. 3: For Rank 1 the DQ resistors are shown for simplicity but are the same physical components as shown on Rank 0. 4: EVENT_n is wired on this design. A standalone SPD may be used as well. No wiring changes are required.
PAGE 9
DTM68104A 8GB - 288-Pin 2Rx8 Unbuffered Non-ECC DDR4 DIMM DATARAM CORPORATION, USA Corporate Headquarters, P.O. Box 7528, Princeton, NJ 08543-7528; Voice: 609-799-0071, Fax: 609-799-6734; www.dataram.com All rights reserved. The information contained in this document has been carefully checked and is believed to be reliable. However, Dataram assumes no responsibility for inaccuracies.