User guide

P5040 DS Hardware Getting Started, Rev. 1.5
22 Freescale Semiconductor
Switch Default Settings
SW8 Configuration
SW8.1: I
2
C1_Force
Controls CPU access to I
2
C1 connected devices owned by ngPIXIS device: FPGA
as well as EEPROM FPGA Configuration Data and EEPROM ExConfiguration Data.
• 0 - System cannot access devices
• 1 - System can access devices [Default]
NOTE!
If SW4.8 = ‘1’ then the CPU accesses above noted devices.
SW8.2: RCW_WP
(RCW Write Protect)
Defines RCW EEPROM WP.
• ‘0’ - No EEPROM WP [Default]
• ’1’ - EEPROM WP
SW8.3: FLASH_WP
(Flash Write Protect)
Defines NOR Flash and SPI Flash memory WP.
• ‘0’ - NOR Flash and SPI Flash memory WP
• ’1’ - No NOR Flash and SPI Flash memory WP [Default]
SW8.4: ID_WP
(ID Write Protect)
Defines EEPROM FPGA Configuration Data WP.
• ‘0’ - No EEPROM WP [Default]
• ’1’ - EEPROM WP
SW8.5: AURORA_CLK_EN
(Aurora Clock Enabled)
• Reserved; not used in P5040/P3041/P05020DS
SW8.6: POVDD_CNTL
(POVDD Control)
Controls POVDD voltage.
• ‘0’ - POVDD=1.5V Ready; [Default]
• ‘1’ - POVDD = 1.0V Ready;
SW8.7: RESET_REQ_MODE
(Reset Request Mode)
Defines reset request mode only if SW7.8 = ‘1’.
• ‘0’ - RESET_REQ asserts HRESET to processor and resets system
• ‘1’- RESET_REQ asserts PORESET to processor and resets system
[Default]
SW8.8: JTAG_AURORA_SEL
(JTAG or Aurora Select)
Controls P5040/P3041/P5020 JTAG port access to COP/JTAG or Aurora
connectors.
• ‘0’ - P5040/P3041/P5020 JTAG port connects to COP/JTAG connector
[Default]
• ‘1’ - P5040/P3041/P5020 JTAG port connects to Aurora connector
8 7 6 5 4 3 2 1
JTAG_AURORA_SEL RESET_REQ_MODE POVDD_CNTL AURORA_CLK_EN ID_WP FLASH_WP RCW_WP
ON ’1’
I2C1_FORCE