User's Manual

dCS 954 User Manual Manual for Standard Software Version 1.5x
dCS Ltd June 2000
Manual part no: DOC136954 iss 2B1
Page 68
file 135954ma2b1.pdf available from website
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G
ENERAL
T
ECHNICAL
I
NFORMATION
Jitter and PLL bandwidths
Jitter and PLL performance are related. In a DAC, in many applications the
clock for the received data has to be extracted from the signal coming into it. To
do this, the DAC has to have circuitry that looks at data edges (edges are the
only things that carry time information), and has to extract enough information
from these to generate an stable internal clock. This stability criterion is much
greater for a DAC, which has to produce an analogue output, than for a piece of
digital equipment – which just has to avoid data corruption.
The task is generally carried out in a phase locked loop (PLL). This controls an
internal oscillator (a VCXO in dCS equipment) such that on average the rate that
this produces clock edges is the same as the rate the incoming signal produces
clock edges (the frequencies are the same), and such that the phases of these
two clocks (incoming and internally generated) is on average fixed – they line up
in the same way each time.
“On average” is the key phrase. The purpose of the PLL is to produce a clean
clock from one that may have come through a lot of digital equipment, and may
not be so good. So, the internal clock has to allow the incoming one to wander
around a bit (jitter) without causing any local upsets. The rate that the internal
one changes if the incoming one changes is related to the bandwidth of the PLL.
If the bandwidth is high, the internal one tracks rapid changes in the incoming
signal, and jitters the output in line with the input accordingly. If the bandwidth is
low, the clock used for reconstituting the analogue signal can be very good and
jitter free, but at any particular time the difference in phase between the two
clocks can be substantial. This can cause decoding errors.
In principle, the lower the PLL bandwidth, the more the DAC clock can be made
independent of the incoming clock, and so the more jitter can be removed. Two
things conspire to limit how far one can go with this process.
The first is “lock in time” – the time it takes the low bandwidth PLL to lock to a
new signal. As the bandwidth reduces this can get very long.
The second is low frequency jitter in the incoming signal. Most signal sources
with reasonable clocks have noise and spuriae in the clock spectrum that
increase as one gets closer to the clock frequency. As one gets very close,
these cause large, slow time excursions – edges wander on a slow basis. At
bandwidths in the Hz area, with sources that involve any form of mechanical
device (storage drives, for example), these can be many hundreds of nsecs,
and if one goes below 1 Hz, they get worse.
Because of these types of issue, dCS use a bandwidth of around 5 Hz for our
PLLs in fine lock. This bandwidth enables jitter in the audio band to be
substantially suppressed, but lock in times do not become excessive. We use a
dual arrangement, with one low bandwidth PLL used to extract the clock (the low
bandwidth one), and a much faster one used to extract the data. The bandwidth
of the data extraction PLL has no effect on audio quality – as long as it extracts
digitally correct data it is doing its job okay. It is capable of correctly extracting
data with quite large time errors, easily meeting the AES3 requirements. Using
this approach, rather than any approach based on FIFOs, ensures that delay
between data coming in and replaying is minimised. If a FIFO approach is used,