Datasheet

Introduction
10 Datasheet Volume 2 of 2
IOH Input/Output Hub. An Intel
®
QuickPath Interconnect agent that handles IO
requests for processors.
IPI Inter-processor interrupt
L1 Cache First-level cache
L2 Cache Second-level cache
LLC Last Level Cache
LVT Local Vector Table
Mapper Address mapper in memory controller is a combinational function which
translates the coherency controller address (Local address) into DIMM specific
row, column, bank addresses.
MC Machine Check
MCA Machine Check Architecture
NB North Bound
NBSP Node Boot Strap Processor (Core). A core within a CPU that is responsible to
execute code to initialize the CPU.
Node Controller Chipset component that enables hierarchical scaling of computing segments by
abstracting them and acting as proxy to those computing segments to build
scalable multi-processor systems.
NodeID 5-bit address field located with in an Intel QuickPath Interconnect packet. Intel
QuickPath Interconnect agents can be uniquely identified through NodeIDs.
NUMA Non Uniform Memory Access
Parity Even parity (even number of ones in data).
PBox Port Physical Interface
PIC Programmable Interrupt Controller
PLL Phase Locked Loop
RAS Row Address Select / Reliability Accessibility Serviceability
RBox Crossbar Router
RTA Router Table Array
SB Southbound
SBox Caching Agent or System Interface Controller
SCMD Sub command
SECDED Single Error Correction Double Error Detection
SMBus System Management Bus. Mastered by a system management controller to read
and write configuration registers. Limited to 100 KHz.
SMM System Management Mode
Socket Processor, CPU (cores + uncore)
SPCL Special
SPI Serial Peripheral Interface
SSP System Service Processor
TLB Translational Lookaside Buffer, present in each core, handles linear to physical
address mapping.
TOCM Top of Intel QuickPath Interconnect Physical Memory
UBox Configuration Agent or System utilities/management controller.
UI Unit Interval, Average time interval between voltage transition of the signals.
Uncore System interface logic
VLW Virtual Legacy Wire
Table 1-1. Abbreviation Summary (Sheet 2 of 3)
Term Description