Datasheet

Power Management Architecture (Wbox)
44 Datasheet Volume 2 of 2
If this is the last enabled thread to enter the C3 or lower state, the Intel Xeon Processor
E7-8800/4800/2800 Product Families flushes the I cache, D cache, and MLC before
putting the thread to sleep. Note that these flush operations are atomic – if a break
event to either thread occurs after the flush of a cache is begun, the flush will
complete.
9.2.2.4.2 Thread/Core C3 Exit
When the core wakes up, the core active bit in the Wbox is set by core hardware. The
core resumes operation at the latest P-state target.
9.2.2.5 Package C3
The package will attempt to enter the package C3 state when all cores have
transitioned to the C3 state or C6 states with at least one core in C3. Once all cores
have entered the C3 state, the Wbox will do system level PMReq negotiation to enter to
Package C3 state and take uncore power saving actions. It sends a PMReq(C3) request
to the platform. If this request is acknowledged with a CmpD(C3) or lower from all Intel
QPI links, the PCU will take further power reduction actions in the uncore. The core
voltage will be reduced to a minimum retention voltage designed to minimize leakage
power while retaining all state values. It will kill the Intel SMI link and do macro clock
gating in some of uncore boxes for power saving.
Once the package has entered the package C3 state, it will be woken when it receives a
core break event. Break events can be forwarded from the system across the Intel
®
QuickPath Interconnect bus, or can be the result of internally generated events (probe
mode, thermal threshold interrupts, and so forth).
When a core break event is received, the Wbox will first raise the core voltage to the
minimum active Vcc, re-lock the core PLL(s) to the corresponding frequency and
forward the break event message. If the break event is not masked in the core, the
core will return to the C0 state. If the break event is masked in the core, the Wbox will
re-enter the package C3 state. Package can exit and re-enter sub-states Intel Memory
Self Refresh and macro clock gating for servicing memory access, snoop, and so forth,
while in package C3 state.
9.2.2.6 I/O Support for C-State Requests
Software may make C-state requests by using a legacy method involving I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
feature is designed to provide legacy support for operating systems that initiate C-state
transitions via access to pre-defined ICH registers. On previous products, the base
P_LVLx register is P_LVL2, corresponding to a C2 request. P_LVL3 is C3 and so forth.
Because Intel Xeon Processor 7500 Series has compressed the C-state encoding space,
P_LVL2 corresponds to a C3 request.
Only 'IN' instructions to the supported P_LVLx addresses will trap and redirect to the
MWAIT C-state flow. ''REP INS'', for example, does not redirect. P_LVL2 is defined in
the PMG_IO_CAPTURE MSR. P_LVLx is limited to a subset of C-states. For example,
P_LVL8 is not supported and will not cause an I/O redirection to a C8 request. Instead,
it will fall through like a normal I/O instruction. The range of I/O addresses that may be
converted into C-state requests is also defined in the PMG_IO_CAPTURE MSR, in the 'C-
state Range' field. This field may be written by BIOS to restrict the range of I/O
addresses that are trapped and redirected to MWAIT instructions. Note that when I/O
instructions are used, no MWAIT substates can be defined, and therefore the request