Datasheet

Power Management Architecture (Wbox)
46 Datasheet Volume 2 of 2
9.4.1 Introduction
The PMReq negotiation is done to enter package C6 state where uncore power
optimization actions are taken.The package will attempt to enter the C6 state when all
cores have transitioned to the C6. Once the package has entered the C6 state, it will
only be woken when it receives a break event, memory transaction or a snoop. It also
wake up from macro-clock gating for some of the PECI transactions which requires
uncore clocks. Break events can be forwarded from the system across the Intel QPI
bus, or can be the result of internally generated events. The processor can exit and re-
enter sub-states, Memory Self Refresh and macro clock gating for servicing memory
access, while in package C6 state.
9.5 Package C3/Package C6 with Memory Self
Refresh
Intel Xeon processor 7500 series-based platform supports the NUMA memory
architecture where access to local memory is much faster than other sockets memory.
The architecture ensures that each socket predominantly access its local memory than
other socket's memory to take benefit of lower access latency. It provides an
opportunity to put Intel SMI port in low power state during package C3 and Package C6
states where all cores in the socket are in deep sleep states leading to significantly low
memory access in these package states. Since local memory can still be accessible by
remove socket at any time (even though infrequently), the uncore needs to detect this
remote memory access and exit from this lower power state to complete transaction
with in acceptable latency. Package C3/C6 with Memory Self Refresh reduces power
across the socket, Intel
®
7510/7512 Scalable Memory Buffer, and DIMMs resulting in
overall platform idle power reduction.
9.5.1 Package C3/C6 Memory Self-Refresh Limitations
9.5.1.1 Firmware Interval Timer
If package C3/C6 is enabled then Firmware interval timer counter will be frozen on
package state entry and unfrozen on exit. The duration of freeze tracks package state
residency and is hence traffic pattern dependent.
9.5.1.2 Error Handling
Packet based error signaling is not supported during package C3/C6 if memory self
refresh is enabled.
• Fatal errors: During package C3/C6 the majority of the processor uncore is
powered down therefore only a small subset of fatal errors are allowed.
Recommend relying on pin based signaling ERR#1.
• Recoverable errors: Error can be logged while in package C3/C6, but the
corresponding Intel SMI packet is generated on a wake-up event that brings the
package out of memory self refresh.
• Uncorrectable errors: None possible when processor is in C3/C6 idle power state.