Reference Guide

12 Statement of Volatility – Dell DR6300, DR4300, DR4300e
Item
How is data input to this
memory?
How is this memory
write protected?
How is the memory cleared?
SEP internal
flash
I2C interface via iDRAC
Program write protect
bit
Not user clearable
Backplane
External FRU
Programmed at ICT during
production.
Not WP
Cannot be cleared with existing tools
available to the customer
12x3.5" EXP/Backplane
NVSRAM
memory
Common Flash memory
Interface (CFI)
Hardware strapping
Not user clearable
Flash memory
Common Flash memory
Interface (CFI)
Hardware strapping
Not user clearable
BP FRU image
I2C interface via expander
Hardware strapping
Not user clearable
Expander FRU
image
I2C interface via iDRAC
Hardware strapping
Not user clearable
18x1.8" Exp/Backplane
NVSRAM
memory
Common Flash memory
Interface (CFI)
Hardware strapping
Not user clearable
Flash memory
Common Flash memory
Interface (CFI)
Hardware strapping
Not user clearable
BP FRU image
I2C interface via expander
Hardware strapping
Not user clearable
Expander FRU
image
I2C interface via iDRAC
Hardware strapping
Not user clearable
H730, H830 PERCs
NVSRAM
ROC writes configuration
data to NVSRAM
Not WP. Not visible to
Host Processor
Cannot be cleared with existing tools
available to the customer
FRU
Programmed at ICT during
production.
Not WP
Cannot be cleared with existing tools
available to the customer
1-Wire EEPROM
ROC writes data to this
memory
Not WP. Not visible to
Host Processor
Cannot be cleared with existing tools
available to the customer
SPD
Pre-programmed before
assembly
Not WP. Not visible to
Host Processor
Cannot be cleared with existing tools
available to the customer
SBR
Pre-programmed before
assembly
Not WP. Not visible to
Host Processor
Cannot be cleared with existing tools
available to the customer