CIM Reference Guide

CIM_LogicalElement 67
CIM_MemoryMappedIO
The CIM_MemoryMappedIO class explained in Table 3-40 addresses both memory and port I/O resources
for personal computer architecture memory mapped I/O.
TriggerType Indicates whether edge (value=4) or level triggered
(value=3) interrupts occur.
1 Other
2 Unknown
3 Level
4 Edge
uint16
Shareable Indicates whether the IRQ can be shared. A value of
TRUE indicates that the IRQ can be shared.
Boolean
Hardware Indicates whether the interrupt is hardware- or
software-based. (A value of TRUE indicates that the
interrupt is hardware based.) On a personal computer,
a hardware IRQ is a physical wire to a programmable
interrupt controller (PIC) chip set through which the
microprocessor can be notified of time critical events.
Some IRQ lines are reserved for standard devices such
as the keyboard, diskette drive, and the system clock.
A software interrupt is a programmatic mechanism to
allow an application to get the attention of
the processor.
Boolean
Table 3-39. CIM_IRQ Properties (continued)
Class Name: CIM_IRQ
Parent Class: CIM_SystemResource
Property Description Data Type
CIM_ManagedSystemElement
CIM_LogicalElement
CIM_SystemResource
CIM_MemoryMappedIO