Reference Guide

Item
How is data input to this
memory?
How is this memory
write protected?
How is the memory cleared?
LOM Flash
SPI interface via i350
NA
Not user clearable
24x2.5" MCU/Backplane
MCU
Pre-programmed before
assembly
Not WP
Not user clearable
Expander BP (RTS+)
SPI Flash
Pre-programmed before
assembly, can be updated
via LSI adapter and LSI
utility
Not WP
Not user clearable
12x3.5" MCU Backplane
MCU
Pre-programmed before
assembly
Not WP
Not user clearable
FCB
H8
Pre-programmed before
assembly, can be updated
via DELL utility
Not WP
Not user clearable
CPLD
Pre-programmed before
assembly
Not WP
Not user clearable
FRU
Pre-programmed before
assembly
Not WP
Not user clearable
Mid-Plane
EEPROM
Pre-programmed before
assembly
Not WP
Not user clearable
H730, PERC (RTS+)
NVSRAM
ROC writes configuration
data to NVSRAM
Not WP. Not visible to
Host Processor
Cannot be cleared with existing tools
available to the customer
FRU
Programmed at ICT during
production.
Not WP
Cannot be cleared with existing tools
available to the customer
1-Wire EEPROM
ROC writes data to this
memory
Not WP. Not visible to
Host Processor
Cannot be cleared with existing tools
available to the customer
SPD
Pre-programmed before
assembly
Not WP. Not visible to
Host Processor
Cannot be cleared with existing tools
available to the customer
SBR
Pre-programmed before
assembly
Not WP. Not visible to
Host Processor
Cannot be cleared with existing tools
available to the customer
Flash
Pre-programmed before
assembly. Can be updated
using Dell/LSI tools
Not WP. Not visible to
Host Processor
Cannot be cleared with existing tools
available to the customer
ONFI Backup
Flash
FPGA backs up DDR data
to this device in case of a
power failure
Not WP. Not visible to
Host Processor
Flash can be cleared by powering up
the card and allowing the controller to
flush the contents to VDs. If the VDs
are no longer available, cache can be
cleared by going into controller bios
and selecting Discard Preserved
Cache.
SDRAM
ROC writes to this
memory - using it as
cache for data IO to HDDs
Not WP. Not visible to
Host Processor
Cache can be cleared by powering off
the card
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