Reference Guide

Item
How is data input to this memory?
How is this memory write protected?
Node iDRAC EMMC
NAND Flash interface via iDRAC
Embedded FW write protected
Node Network EEPROM
SPI interface via CPU nodes
Software Write Protected
Fabric A Switch EEPROM
SPI interface via iDRAC
Software Write Protected
Fabric D Switch EEPROM
SPI interface via iDRAC
N/A- Controlled by the Chassis
Management Controller (CMC)
CPLD RAM
Not utilized
Not accessible
System Memory
System OS RAM
System OS
System Memory
System OS
OS Control
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