Reference Guide

Dell - Internal Use - Confidential
Item
How is data input to this
memory?
How is this memory write
protected?
How is the memory
cleared?
SDRAM
ROC writes to this memory
- using it as cache for data
IO to HDDs
no write protected. Not
visible to Host Processor
Cache can be cleared by
powering off the card
HBA355i fPERC
NVSRAM
ROC writes configuration
data to NVSRAM
no write protected. Not
visible to Host Processor
User cannot clear the
memory.
FRU
Programmed at ICT during
production.
no write protected
User cannot clear the
memory.
Flash
Pre-programmed before
assembly. Can be updated
using Dell/LSI tools
no write protected. Not
visible to Host Processor
User cannot clear the
memory.
Left Status CP
Microcontroller
I2C via iDRAC
Hardware strapping
User cannot clear the
memory.
Left Titan2
Microcontroller
SPI interface via iDRAC
Hardware strapping
User cannot clear the
memory.
TPM
Trusted Platform Module
(TPM)
Using TPM Enabled
operating systems
SW write protected
F2 Setup option
Right FIO 1U Package 1
SPI Flash
SPI interface from iDRAC
to Right Cntl Panel
Embedded iDRAC
subsystem firmware
actively controls sub area
based write protection as
needed.
The user cannot clear
memory.
IDSDM
iDSDM (uSD1, uSD2)
device resides in host
domain; they are exposed
to the user via an
internally connected, non-
removable USB mass
storage device
physical write protect
switch on ACE card
(1) card may be physically
removed and destroyed
or cleared via standard
means on a separate
computer OR
(2)User has access to the
card in the host domain
and may clear it manually
SPI Flash
User can initiate a
firmware update of the
IDSDM device.
There is no mechanism
provided to iDRAC to write
any SPI NOR area outside
of the primary IDSDM
firmware region.
iDRAC may issue a clear
command to erase all
contents of the SPI NOR,
but doing this will leave
the IDSDM non-
functional.
BOSS-S1
SPI FLASH
By programming the
image via firmware update
process
N/A
Use Flash tool, type
“go.nsh w y”
TFRU
During Manufacturing, by
programming the image
via firmware update
process.
During runtime, by I2C
Proprietary Command
Protocol
N/A
By writing to Flash