Reference Guide

Item
How is this memory write
protected?
How is the memory cleared?
Planer
PCH Internal CMOS RAM
N/A – BIOS only control
1) Set NVRAM_CLR jumper to clear BIOS
configuration settings at boot and reboot system;
2) AC power off system, remove coin cell battery
for 30 seconds, replace battery and power back
on; 3) restore default configuration in F2 system
setup menu.
BIOS Password
N/A
Place shunt on J_PSWD_NVRAM jumper pins 2
and 4.
BIOS SPI Flash
Software write protected
Not possible with any utilities or applications and
system is not functional if corrupted/removed.
iDRAC SPI Flash
Embedded iDRAC
subsystem firmware
actively controls sub area
based write protection as
needed.
Not completely user clearable; however, user
data, lifecycle log and archive, SEL, fw image
repository can be cleared via Delete
Configuration and Retire System, accessible in
Lifecycle Controller interface
BMC EMMC
Embedded FW write
protected
Not completely user clearable; however, user
data, lifecycle log and archive, SEL, fw image
repository can be cleared via Delete
Configuration and Retire System, accessible in
Lifecycle Controller interface
System CPLD RAM
Not accessible
Not accessible
System Memory
OS Control
Reboot or power down system
Internal USB Key
No write protect
Can be cleared in system OS
Trusted Platform Module
(TPM, TPM 2.0 only)
SW write protected
F2 Setup option
CPU
Various
Power off
iDRAC DDR
NA
Power off
iDRAC
NA
Power off
Power Supplies
PSU FW
Protected by the
embedded microcontroller.
Special keys are used by
special vendor provided
utilities to unlock the ROM
with various CRC checks
during load.
Not clearable
12x3.5" Backplane
NVSRAM memory
Hardware strapping
Not user clearable