Reference Guide

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Statement of Volatility – Dell EMC PowerEdge – R6515

Dell EMC PowerEdge R6515 contains both volatile and non-volatile (NV) components. Volatile components lose

their data immediately upon removal of power from the component. Non-volatile components continue to retain

their data even after the power has been removed from the component. Components chosen as user-definable

configuration options (those not soldered to the motherboard) are not included in the Statement of Volatility.

Configuration option information (pertinent to options such as microprocessors, remote access controllers, and

storage controllers) is available by component separately. The following NV components are present in the

PowerEdge R6515 server.

Item

Non-Volatile

or Volatile

Quantity

Reference Designator

Size

Planar

CPU Internal CMOS

RAM

Non-Volatile

CPU0

256M bytes

BIOS SPI Flash

Non-Volatile

J6_1

32 MB

iDRAC SPI Flash

Non-Volatile

J5_1

4 MB

BMC EMMC

Non-Volatile

U_EMMC2

8 GB

System CPLD RAM

Volatile

U_CPLD1

34 KB

System Memory

Volatile

CPU0: A1~A16,

Up to 64GB per DIMM

(RDIMM)

Up to 128GB per DIMM

(LRDIMM)

CPU Vcore and

VDDCR SOC FW

Non-Volatile

PAAU1 PBAU1

MEM_VDDQ FW

Non-Volatile

PAEU1, PBEU1

LOM NVRAM

Non-Volatile

U_LOM1_ROM

8MB

Power Supplies

PSU FW

Non-Volatile

1 per PSU

Varies by part number

Up to 2MB. Varies by part

number

Summary of content (3 pages)

PAGE 1
Statement of Volatility – Dell EMC PowerEdge – R6515 Dell EMC PowerEdge R6515 contains both volatile and non-volatile (NV) components. Volatile components lose their data immediately upon removal of power from the component. Non-volatile components continue to retain their data even after the power has been removed from the component. Components chosen as user-definable configuration options (those not soldered to the motherboard) are not included in the Statement of Volatility.
PAGE 2
Type (e.g. Flash PROM, EEPROM) Can user programs or operating system write data to it during normal operation? Purpose? (e.g.
PAGE 3
Item How is data input to this memory? How is this memory write protected? CPU Internal CMOS RAM BIOS N/A – BIOS only control BIOS SPI Flash SPI interface via iDRAC Software write protected iDRAC SPI Flash SPI interface via iDRAC Embedded iDRAC subsystem firmware actively controls sub area based write protection as needed.