Reference Guide

Table 5. Processor Settings details (continued)
Option Description
displays only one logical processor per core. This option is set
to Enabled by default.
Virtualization Technology Enables or disables the virtualization technology for the
processor. This option is set to Enabled by default.
IOMMU Support Enable or Disable IOMMU support. It is required to create
IVRS ACPI table. This option is set to Enabled by default.
L1 Stream HW Prefetcher Enables or disables the L1 stream hardware prefetcher. This
option is set to Enabled by default.
L2 Stream HW Prefetcher Enables or disables the L2 stream hardware prefetcher. This
option is set to Enabled by default.
L1 Stride Prefetcher Enables or disables the L1 stride prefetcher. This option is set
to Enabled by default, as it optimizes overall workload.
L1 Region Prefetcher Enables or disables the L1 region prefetcher. This option is set
to Enabled by default, as it optimizes overall workload.
L2 Up Down Prefetcher Enables or disables the L2 up down prefetcher. This option is
set to Enabled by default, as it optimizes overall workload.
MADT Core Enumeration Specifies the MADT Core Enumeration. This option is set to
Linear by default.
NUMA Nodes Per Socket Specifies the number of NUMA nodes per socket. This option
is set to 1 by default.
L3 cache as NUMA Domain Enables or disables the CCX as NUMA Domain. This option is
set to Disabled by default.
Secure Memory Encryption (SME) Enables or disables the AMD secure encryption features such
as SME and Secure Encrypted Virtualization (SEV). It also
determines if other secure encryption features such as TSME
and SEV-SNP can be enabled. This option is set to Disabled
by default.
Minimum SEV non-ES ASID Determines the number of Secure Encrypted Virtualization ES
and non-ES available Address Space IDs. This option is set to
1 by default.
Secured Nested Paging (SNP) Enables or disables SEV-SNP, a set of additional security
protections. This option is set to Disabled by default.
Transparent Secure Memory Encryption (TSME) Enables or disables the TSME. TSME is always-on memory
encryption that does not require OS or hypervisor support.
This option is set to Disabled by default.
● If the OS supports SME, do not enable this field.
● If the hypervisor supports SEV, do not enable this field.
Enabling TSME affects the system memory performance.
x2APIC Mode Enable or disable x2APIC mode. This option is set to Enabled
by default.
NOTE: For two CPU 64 cores configuration, x2APIC
mode is not switchable if 256 threads are enabled (BIOS
settings: All CCD, cores, and logical processors enabled).
Number of CCDs per Processor Controls the number of enabled CCDs in each processor. This
option is set to All by default.
Number of Cores per CCD specifies the number of cores per CCD. This option is set to
All by default.
Processor Core Speed Specifies the maximum core frequency of the processor.
Pre-operating system management applications 7