Owners Manual

 
Address
Translation
Services (ATS(



  Address Translation Cache (ATC (






 

  DMA   







 . 
     

    

 DMA

 

 .





 

 

 

.
Adjacent Cache
Line Prefetch


 

 








 



 

 

   



.





 



 Adjacent Cache Line
Prefetch 

 .



  

 










 

 

   

  .
Hardware
Prefetcher

 



  







.





 



Hardware Prefetcher 

.
DCU Streamer
Prefetcher





 



 Data Cache Unit (DCU) streamer prefetcher .





DCU Streamer
Prefetcher 



 

.
DCU IP Prefetcher

 



 Data Cache Unit (DCU) streamer prefetcher .





DCU IP Prefetcher 






.
Execute Disable

 







  .









 Execute Disable

.
Logical Processor
Idling

 



 





   



  



    .





 

 

 

.
Configurable TDP





  Thermal Design Power (TDP (




.
TDP





 



  

  







.
X2Apic Mode 

 



  X2Apic
Dell Controlled
Turbo
 :

     




   

   ..

 





.

  

 

 



 System Profile  

.
Number of Cores
per Processor

   

     .





 



 Number of Cores per Processor  .
Processor 64-bit
Support
  

  )  ( 

 64 .
Processor Core
Speed
 

  

 .
Processor 1
 :

     




   

 

   .  

 



  





.
Family-Model-
Stepping
   

       Intel.
Brand   

  .
Level 2 Cache   

  L2
Level 3 Cache   

  L3
Number of Cores 



 .
Processor 2
 :

     




   

 

   .  

 



  





.
Family-Model-
Stepping
   

       Intel.
Brand   

  .
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