Release Notes

4 Balanced Memory with 2
nd
Generation AMD EPYC
TM
Processors for PowerEdge Servers
1. Introduction
Understanding the relationship between a server processor (CPU) and its memory
subsystem is critical when optimizing overall server performance. Every processor
generation has a unique architecture, with volatile controllers, channels and slot
population guidelines, that must be satisfied to attain high memory bandwidth and low
memory access latency.
2
nd
Generation AMD EPYC
TM
server processors, which will be referred to by their code
name throughout this white paper, Rome processors, offer a total of eight memory
channels with up to two memory slots per channel.
1
This presents numerous possible
permutations for configuring the memory subsystem with traditional Dual In-Line
Memory Modules (DIMMs), yet there are only a couple of balanced configurations that
will achieve the peak memory performance for Dell EMC PowerEdge servers.
Memory that has been incorrectly populated is referred to as an unbalanced
configuration. From a functionality standpoint, an unbalanced configuration will operate
adequately, but introduces significant additional overhead that will slow down data
transfer speeds. Similarly, a near balanced configuration does not yield fully optimized
data transfer speeds but it is only suboptimal to that of a balanced configuration.
Conversely, memory that has been correctly populated is referred to as a balanced
configuration and will secure optimal functionality and data transfer speeds.
This white paper explains how to balance memory configured for Rome processors
within Dell EMC PowerEdge servers.