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20 | Whitepaper – Exploring Computing Platforms for Radio Access

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be seen in Table 1, which shows normalized cycles attributable to the uplink decode and the

downlink encode.

As with any real-time computing task, another important timing consideration is the deviation in

processing time. In datacenter applications, this has been called the “long tail” in latency. This

test setup was not equipped to measure the standard deviation, however the maximum duration

was captured for the thread that performs the interleaving portion of the Turbo algorithm. (See

reference

for a description brief description of the algorithm and the IP.) This was measured

over a million iterations (time transmission intervals, which is 1ms for LTE) in the test setup of

Figure 22. The variation in processing time between the average and maximum thread duration

in the offloaded case was only 15% that of the software-only case.

Figure 22: Turbo FEC execution times (results with and without FPGA offload)

normalized cycles -

without offload

normalized cycles - with

Turbo offload

% hardware assisted

cycles vs. software-only

test case description

total L1

UL+DL

Turbo

FEC

Turbo

FEC

total L1

UL+DL

Turbo

FEC

Turbo

FEC

DL Turbo

FEC

UL Turbo

FEC

1 cell, 4 antennas, 8 CW

QAM64, TB=4395 Bytes

1.00

0.27

0.25

0.55

0.03

10.2%

13.5%

Table 1: CPU cycle comparison on Turbo operations with and without FPGA offload