User's Manual

DFZM-E72xx
Data Sheet Sheet 11 of 40 Sep 16, 2013
Proprietary Information and Specifications are Subject to Change
The DFZM-E72xx’s power management system is designed to achieve the lowest deep sleep current consumption
possible while still providing flexible wakeup sources, timer activity, and debugger operation. The DFZM-E72xx
has four main sleep modes:
 Idle Sleep: Puts the CPU into an idle state where execution is suspended until any interrupt occurs. All power
domains remain fully powered and nothing is reset.
 Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is fully powered down and
the sleep timer is active.
 Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to save power. In this mode the
sleep timer cannot wake up the DFZM-E72xx.
 Deep Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep sleep without powering
down the core domain. Instead, the core domain remains powered and all peripherals except the system debug
components (ITM, DWT, FPB, NVIC) are held in reset. The purpose of this sleep state is to allow DFZM-E72xx
software to perform a deep sleep cycle while maintaining debug configuration such as breakpoints.
The power management state diagram in Figure 3-5 shows the basic operation of the power management
controller.
Figure 3-5: DFZM-E72xx power management state diagram