User's Manual

DFZM-E82xx

Data Sheet Sheet 21 of 41 Dec 31, 2013

Proprietary Information and Specifications are Subject to Change

TRACEDATA0 O

Synchronous CPU trace data bit 3 , Select 4-wire synchronous trace interface in ARM

core , Enable trace interface in ARM core , Select alternate output function with

GPIO_PCCFGL[11:8].

PC3 I/O

Digital I/O, Either Enable with GPIO_DBGCFG[5]

or enable Serial Wire mode (see JTMS description)

JTDI I

JTAG data in from debugger

Selected when in JTAG mode (default mode, see JTMS description, Pin 35)

Internal pull-up is enabled

TRACECLK O

Synchronous CPU trace clock , Enable trace interface in ARM core , Select alternate

output function with GPIO_PCCFGL[15:12].

PC4 I/O Digital I/O, Enable with GPIO_DBGCFG[5]

JTMS I

JTAG mode select from debugger, Selected when in JTAG mode (default mode)

JTAG mode is enabled after power-up or by forcing nRESET low

Select Serial Wire mode using the ARM-defined protocol through a debugger

Internal pull-up is enabled

SWDIO I/O

Serial Wire bidirectional data to/from debugger

Enable Serial Wire mode (see JTMS description)

Select Serial Wire mode using the ARM-defined protocol through a debugger

Internal pull-up is enabled

PB0 I/O Digital I/O(Not available for DFZM-E821X-DT0R)

VREF Analog O ADC reference output, Enable analog function with GPIO_PBCFGL[3:0]

VREF Analog I

ADC reference input, Enable analog function with GPIO_PBCFGL[3:0]

Enable reference output with an Ember system function

IRQA I External interrupt source A

TRACEDATA2 O

Synchronous CPU trace data bit 2

Select 4-wire synchronous trace interface in ARM core

Enable trace interface in ARM core,

Select alternate output function with GPIO_PCCFGL[3:0]

TIM1CLK I Timer 1 external clock input

TIM2MSK I Timer 2 external clock mask input

23 PC1 I/O Digital I/O