Reference Manual

PMAC 2 Software Reference
114 PMAC I-Variable Specifiation
The following table lists the possible values of Ix81 for the ACC-49:
Enc. #
on
Board
Ix81 for
E1 ON
Ix81 for
E2 ON
Ix81 for
E3 ON
Enc. #
on
Board
Ix81 for
E4 ON
Ix81 for
E5 ON
Ix81 for
E6 ON
Enc. 1 $0DFFD0 $0DFFD8 $0DFFE0 Enc. 3 $0DFFE8 $0DFFF0 $0DFFF8
Enc. 2 $0DFFD4 $0DFFDC $0DFFE4 Enc. 4 $0DFFEC $0DFFF4 $0DFFFC
MACRO R/D Read: If Ix81 contains a value of $73000n, Motor x will read the absolute
phase position from an ACC-8D Opt. 7 Resolver-to-Digital Converter through a MACRO
Station or compatible device.
In this mode, the last hex digit ‘n’ of Ix81 specifies the MACRO node number. MACRO
Station setup variable MI11x for the matching node must be set to read the R/D converter.
MACRO Parallel Read: If Ix81 contains a value of $74000n, Motor x will read the
absolute phase position from a parallel data source through a MACRO Station or
compatible device.
In this mode, the last hex digit ‘n’ of Ix81 specifies the MACRO node number. MACRO
Station setup variable MI11x for the matching node must be set to read the parallel data
source.
Hall Sensor Read: If Ix81 contains a value from $80xxxx to $FFxxxx (bit 23 if Ix81 set to
1), Motor x will read bits 20 through 22 of the PMAC memory or I/O register at the
address specified by the low sixteen bits (last 4 hex digits ‘xxxx’) of Ix81. It will expect
these three bits to be encoded as the U, V, and W “hall-effect” commutation signals with
120
o
e spacing for the absolute power-on phase position. In this mode, the address
specified in Ix81 is usually that of a flag register.
If the flag register is in a PMAC(1) or PMAC(1)-style ACC-24P, the flag inputs for bits
20, 21, and 22, representing W, V, and U, are +LIMn, -LIMn, and HMFLn, respectively.
In a typical application, Ix81 specifies that these inputs are used from the “spare” flag
register matching the second DAC channel used for commutation.
The following table shows the Ix81 settings for the flag registers in even-numbered
channels of a PMAC(1) and a PMAC(1)-style ACC-24P that are typically used for hall
commutation sensor inputs:
Channel Ix81 Channel Ix81
2 $xxC004 10 $xxC024
4 $xxC00C 12 $xxC02C
6 $xxC014 14 $xxC034
8 $xxC01C 16 $xxC03C
The proper value of ‘xx’ depends on the offset and direction sense of
the hall sensors.
If the flag register is in a PMAC2-style Servo IC, the input flags for bits 20, 21, and 22,
representing W, V, and U, are CHWn, CHVn, and CHUn, respectively. In a typical
application, these inputs are used from the same flag register addressed by Ix25 for the
main flags.