Reference Manual

PMAC 2 Software Reference
PMAC I-Variable Specification 115
The following table shows the Ix81 settings for the flag registers in channels of a PMAC2
that are typically used for hall commutation sensor inputs:
Channel Ix81 Channel Ix81
1 $xxC000 5 $xxC020
2 $xxC008 6 $xxC028
3 $xxC010 7 $xxC030
4 $xxC018 8 $xxC038
The proper value of ‘xx’ depends on the offset and direction sense of
the hall sensors.
In this mode, bit 22 of Ix81 allows for reversal of the sense of the hall-effect sensors. If W
(bit 20 of the register; HMFLn or CHWn) leads V (bit 21; -LIMn or CHVn), and V leads
U (bit 22; +LIMn or CHUn) as the commutation cycle counts up, then bit 22 of Ix81
should be set to 0. If U leads V and V leads W as the commutation cycle counts up, then
bit 22 of Ix81 should be set to 1.
In this mode, bits 16 to 21 of Ix81 together form an offset value from 0 to 63 representing
the difference between PMAC’s commutation cycle zero and the hall-effect sensor zero
position, which is defined as the transition of the V signal when U is low. This offset has
units of 1/64 of a commutation cycle, or 5.625
o
e. Typically, one of the transitions will be
at PMAC’s commutation zero point, so the desired offset values will be 0
o
, 60
o
, 120
o
, 180
o
,
240
o
, and 300
o
, approximated by values of 0, 11($0B), 21($15), 32($20), 43($2B), and
53($35).
This operation can handle hall-effect sensors separated by 120
o
e. The following table
gives the Ix81 settings for bits 16 to 23 for the most common cases of hall-effect settings
as they relate to the PMAC commutation cycle.
0 to
60 deg
60 to
120deg
120 to
180 deg
180 to
-120 deg
-120 to
-60 deg
-60 to
0 deg
Ix81
011 010 110 100 101 001 $80xxxx
001 011 010 110 100 101 $8Bxxxx
101 001 011 010 110 100 $95xxxx
100 101 001 011 010 110 $A0xxxx
110 100 101 001 011 010 $ABxxxx
010 110 100 101 001 011 $B5xxxx
001 101 100 110 010 011 $C0xxxx
011 001 101 100 110 010 $CBxxxx
010 011 001 101 100 110 $D5xxxx
110 010 011 001 101 100 $E0xxxx
100 110 010 011 001 101 $EBxxxx
101 100 110 010 011 001 $F5xxxx
Note that ‘000’ and ‘111’ are invalid readings.
Example
Motor 1 has a single resolver at location 0 of an ACC-8D Opt.7 R/D converter board at
multiplex address 0; no phasing search is permitted, but a homing search is required:
I181=$000100 ($100=256dec, representing multiplex address 0), I110=0.
Motor 2 has a single resolver at location 6 of an ACC-8D Opt 7 board at multiplex address
4; no phasing search is permitted, but a homing search is required: I281=$060004; I210=0.
Motor 3 has a double geared resolver at locations 2 and 3 of an ACC-8D Opt 7 board at
multiplex address 6, with a 10:1 gear ratio between them; no phasing search or homing
search is permitted: I381=$020006; I310=$020006; I93=10