Reference Manual

PMAC 2 Software Reference

128 PMAC I-Variable Specifiation

I901, I906, ..., I976 Encoder n Filter Disable “Encoder I-Variable 1” {PMAC(1) Only}

Range

0 .. 1

Units

none

Default

Remarks

This parameter controls whether the encoder channel enables or disables its digital delay

filter. The options are:

0 = Encoder n digital delay filter enabled

1 = Encoder n digital delay filter disabled (bypassed)

The filter is a 3-stage digital delay filter with best-2-of-3 voting to help suppress noise

spikes on the input lines. It does introduce a small delay into the signal, which can be

unacceptable if the motor is using interpolated sub-count parallel data input, because of

loss of synchronization between the quadrature and parallel data signals.

Note:

Generally, the only people to disable this filter are those using the

special interpolated parallel data format. These people should

disable the filters both on the encoder for their quadrature signals

and the encoder matching their parallel data input.

The sampling frequency for the filter is that of the SCLK signal, which is set by the master

clock frequency and jumpers E34-E38. The higher the frequency of SCLK, the higher the

possible count rate, but the narrower the pulse that can be filtered out. SCLK should be set

to allow the maximum expected encoder frequency, but no faster, in order to provide the

maximum noise protection.