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PMAC 2 Software Reference

PMAC I-Variable Specification 135

The pulse-frequency-modulation clock PFM_CLK controls the PFM circuitry that is

commonly used for stepper drives. The maximum pulse frequency possible is 1/4 of the

PFM_CLK frequency. The PFM_CLK frequency should optimally be set to the lowest

value that can generate pulses at the maximum frequency required.

The DAC_CLK controls the serial data frequency into D/A converters. If these converters

are on Delta Tau-provided accessories, the DAC_CLK setting should be left at the default

value.

The ADC_CLK controls the serial data frequency from A/D converters. If these

converters are on Delta Tau-provided accessories, the ADC_CLK setting should be left at

the default value.

To determine the clock frequencies set by a given value of I903, use the following

procedure:

1. Divide I903 by 512 and round down to the nearest integer. This value N1 is the

ADC_CLK divider.

2. Multiply N1 by 512 and subtract the product from I903 to get I903’. Divide I903’ by

64 and round down to the nearest integer. This value N2 is the DAC_CLK divider.

3. Multiply N2 by 64 and subtract the product from I903’ to get I903’’. Divide I903’’ by

8 and round down to the nearest integer. This value N3 is the PFM_CLK divider.

Multiply N3 by 8 and subtract the product from I903’’. The resulting value N4 is the

SCLK divider.

Example

The maximum encoder count frequency in the application is 800 kHz, so the 1.2288 MHz

SCLK frequency is chosen. A pulse train up to 500 kHz needs to be generated, so the

2.4576 MHz PFM_CLK frequency is chosen. The default serial DACs and ADCs

provided by Delta Tau are used, so the default DAC_CLK frequency of 4.9152 MHz and

the default ADC_CLK frequency of 2.4576 MHz are chosen. From the table:

..........................SCLK Divider N: 5

..........................PFM_CLK Divider N: 4

..........................DAC_CLK Divider N: 3

..........................ADC_CLK Divider N: 4

..........................I903 = 5 + (8 * 4) + (64 * 3) + (512 * 4) = 5 + 32 + 192 + 2048 = 2277

I903 has been set to 3429. What clock frequencies does this set?

..........................N1 = INT (3429/512) = 6 ADC_CLK = 611.44 kHz

..........................I903’ = 3429 - (512*6) = 357

..........................N2 = INT (357/64) = 5 DAC_CLK = 1.2288 MHz

..........................I903’’ = 357 - (64*5) = 37

..........................N3 = INT (37/8) = 4 PFM_CLK = 2.4576 MHz

..........................N4 = 37 - (8*4) = 5 SCLK = 1.2288 MHz