Reference Manual

PMAC 2 Software Reference
PMAC I-Variable Specification 137
I906 PWM 5-8 Frequency Control {PMAC2 only}
Range
0 .. 32767
Units
PWM Frequency = 117,964.8 kHz / [4*I906+6]
Default
6257
PWM Frequency = 117,964.8 / 26114 = 4.5163 kHz
Remarks
I906 controls the PWM frequency for machine interface channels 5-8. It does this by
setting the limits of the PWM up-down counter, which increments and decrements at the
PWMCLK frequency of 117,964.8 kHz (117.9648 MHz).
The PWM frequency determines the actual switching frequency of amplifiers connected to
any of PMAC2’s first four machine interface channels with the direct PWM command.
The value of I906 is only important if the direct PWM command signal format is used on
channels 5 to 8.
Generally, I906 is set to the same value as I900, which controls the frequency of channels
1 to 4. If a different PWM frequency is desired for channels 5 to 8, I906 should be set so
that
}Integer{
PhaseFreq
)kHz(Freq]85[PWM*2
=
−
This will keep the PWM hardware on channels 5-8 in synchronization with the software
algorithms driven by the PHASE clock, which is set by I900, I901, and I902. For example
if the phase frequency is 10 kHz, the PWM frequency for channels 5 to 8 can be 5, 10, 15,
20, (etc.) kHz.
To set I906 for a desired PWM frequency, the following formula can be used:
1
)kHz(Freq_PWM*4
)kHz(8.964,117
906I −= (rounded down)
Example
A 30 kHz PWM frequency is desired for Channels 5-8:
I906 = (117,964.8 / [4 * 30]) - 1 = 982
See Also
I900, I992
I907 Hardware Clock Control Channels 5-8 {PMAC2 only}
Range
0 .. 4095
Units
I907 = Encoder SCLK Divider
..........................+ 8 * PFM_CLK Divider
..........................+ 64 * DAC_CLK Divider
..........................+ 512 * ADC_CLK Divider
where:...............
Encoder SCLK Frequency = 39.3216 MHz / (2 ^ Encoder SCLK Divider)
PFM_CLK Frequency = 39.3216 MHz / (2 ^ PFM_CLK Divider)
DAC_CLK Frequency = 39.3216 MHz / (2 ^ DAC_CLK Divider)
ADC_CLK Frequency = 39.3216 MHz / (2 ^ ADC_CLK Divider)
Default
2258 = 2 + (8 * 2) + (64 * 3) + (512 * 4)
Encoder SCLK Frequency = 39.3216 MHz / (2 ^ 2) = 9.8304 MHz
PFM_CLK Frequency = 39.3216 MHz / (2 ^ 2) = 9.8304 MHz
DAC_CLK Frequency = 39.3216 MHz / (2 ^ 3) = 4.9152 MHz
ADC_CLK Frequency = 39.3216 MHz / (2 ^ 4) = 2.4576 MHz