Reference Manual

PMAC 2 Software Reference
PMAC I-Variable Specification 149
PWM Frequency = 117,964.8 / 26114 = 4.5173 kHz
Note:
On PMAC2 boards that are not “Ultralite”, I992 does not control
the MaxPhase frequency; I900 does. On all PMAC2 boards, the
PWM 1*-2* frequency is only important if you are using
supplemental PWM channels.
Remarks
I992 controls the maximum phase clock frequency for the PMAC2 Ultralite, and the PWM
frequency for supplementary machine interface channels 1* and 2*. It does this by setting
the limits of the PWM up-down counter, which increments and decrements at the
PWMCLK frequency of 117,964.8 kHz (117.9648 MHz).
The actual phase clock frequency is divided down from the maximum phase clock
according to the setting of I997. On the falling edge of the phase clock, PMAC2 Ultralite
starts transmission of a set of MACRO ring data and interrupts the processor to start any
necessary phase commutation and digital current-loop algorithms. Even if phasing and
current-loop algorithms are not used, the MaxPhase and Phase clock frequencies are
important because the servo clock is derived from the phase clock.
To set I992 for a desired “maximum phase” clock frequency, the following formula can be
used:
I992 = (117,964.8 kHz / [2*MaxPhase (kHz)]) - 1 (rounded down)
On PMAC2 boards that are not “Ultralite”, I992 is generally set to the same value as I900,
which controls the maximum phase frequency, and the PWM frequency of channels 1 to 4.
If a different PWM frequency is desired for channels 1* and 2*, I992 should be set so that
}Integer{
PhaseFreq
)kHz(Freq*]2*1[PWM*2
=
−
Example
To set a PWM frequency of 10 kHz and therefore a MaxPhase clock frequency of 20 kHz:
I992 = (117,964.8 kHz / [4*10 kHz]) - 1 = 2948
To set a PWM frequency of 7.5 kHz and therefore a MaxPhase clock frequency of 15 kHz:
I992 = (117,964.8 kHz / [4*7.5 kHz]) - 1 = 3931
I993 Hardware Clock Control Channels 1*-2* {PMAC2 only}
Range
0 .. 4095
Units
I993 = Encoder SCLK Divider
..........................+ 8 * PFM_CLK Divider
..........................+ 64 * DAC_CLK Divider
..........................+ 512 * ADC_CLK Divider
..........................where:
Encoder SCLK Frequency = 39.3216 MHz / (2 ^ Encoder SCLK Divider)
PFM_CLK Frequency = 39.3216 MHz / (2 ^ PFM_CLK Divider)
DAC_CLK Frequency = 39.3216 MHz / (2 ^ DAC_CLK Divider)
ADC_CLK Frequency = 39.3216 MHz / (2 ^ ADC_CLK Divider)
Default
2258 = 2 + (8 * 2) + (64 * 3) + (512 * 4)
Encoder SCLK Frequency = 39.3216 MHz / (2 ^ 2) = 9.8304 MHz
PFM_CLK Frequency = 39.3216 MHz / (2 ^ 2) = 9.8304 MHz
DAC_CLK Frequency = 39.3216 MHz / (2 ^ 3) = 4.9152 MHz