Reference Manual

PMAC 2 Software Reference
150 PMAC I-Variable Specifiation
ADC_CLK Frequency = 39.3216 MHz / (2 ^ 4) = 2.4576 MHz
Remarks
I993 controls the frequency of three hardware clock frequencies – SCLK, PFM_CLK, and
ADC_CLK – for the supplemental machine interface channels 1* and 2* on PMAC2 or
PMAC2 Ultralite (there is no DAC_CLK on the supplemental channels, but it is referred to
here for consistency with I903 and I907). It is a 12-bit variable consisting of four
independent 3-bit controls (the 3 bits for DAC_CLK are “don’t care”), one for each of the
clocks. Each of these clock frequencies can be divided down from a starting 39.3216 MHz
frequency by powers of 2, 2
N
, from 1 to 128 times (N=0 to 7). This means that the
possible frequency settings for each of these clocks are:
Frequency Divide by Divider N
in 1/2
N
39.3216 MHz 1 0
19.6608 MHz 2 1
9.8304 MHz 4 2
4.9152 MHz 8 3
2.4576 MHz 16 4
1.2288 MHz 32 5
614.4 kHz 64 6
307.2 kHz 128 7
Very few PMAC2 users will be required to change the setting of I993 from the default
value.
The encoder sample clock signal SCLK controls how often PMAC2’s digital hardware
looks at the handwheel encoder inputs. PMAC2 can take at most one count per SCLK
cycle, so the SCLK frequency is the absolute maximum encoder count frequency. SCLK
also controls the signal propagation through the digital delay filters for the encoders and
flags; the lower the SCLK frequency, the greater the noise pulse that can be filtered out.
The SCLK frequency should optimally be set to the lowest value that can accept encoder
counts at the maximum possible rate.
The pulse-frequency-modulation clock PFM_CLK controls the PFM circuitry that can
create pulse and direction outputs on the JHW connector. The maximum pulse frequency
possible is 1/4 of the PFM_CLK frequency. The PFM_CLK frequency should optimally
be set to the lowest value that can generate pulses at the maximum frequency required.
The ADC_CLK controls the serial data frequency from A/D converters. These can only be
accessed as the alternate use of general-purpose I/O pins.
To determine the clock frequencies set by a given value of I993, use the following
procedure:
1. Divide I993 by 512 and round down to the nearest integer. This value N1 is the
ADC_CLK divider.
2. Multiply N1 by 512 and subtract the product from I993 to get I993’. Divide I993’ by
64 and round down to the nearest integer. This value N2 is the DAC_CLK divider
(not relevant here).
3. Multiply N2 by 64 and subtract the product from I993’ to get I993’’. Divide I993’’ by
8 and round down to the nearest integer. This value N3 is the PFM_CLK divider.
4. Multiply N3 by 8 and subtract the product from I993’’. The resulting value N4 is the