Reference Manual

PMAC 2 Software Reference
154 PMAC I-Variable Specifiation
Bits 16-19 together specify the slave number part of the packet address (0-15) that will
cause a sync lock pulse on the card, if this function is enabled by I995. This function is
useful for a PMAC2 that is a slave or non-synchronizing master on the ring, to keep it
locked to the synchronizing master. If the master address check for this node is disabled
with I995, only the slave number must match to create the sync lock pulse. If the master
address check is left enabled, the master number part of the packet address must match the
master number for the card, as set in bits 20-23 of I996.
If this card is the synchronizing master, this function is not enabled, so the value of these
bits does not matter; they can be left at the default of 0.
Bits 20-23 specify the master number for the card (0-15). The number must be specified
whether the card is a master station or a slave station.
B i t
H e x ( $ ) 0 0 0
0 0 0
S l a v e n o d e E n a b l e s
S y n c n o d e
A
d d r e s s
M a s t e r
A
d d r e s s ( 0 - 1 5 )
( 0 - 1 5 )
Note:
On prototype PMAC2 boards that did not support multi-master
MACRO rings, I996 contained only bits 0-15.
Example
Master number 0; Sync node address 0
Activated nodes 0-5; De-activated nodes 6-15:
I996 =0000 0000 0000 0000 0011 1111 (binary) = $00003F
Master number 1; Sync node address 15 ($F)
Activated nodes 0, 2, 4, 6, 8, 10, 12; other nodes de-activated:
I996 = 0001 1111 0001 0101 0101 0101 (binary) = $1F1555
I997 Phase Clock Frequency Control {PMAC2 only}
Range
0 .. 15
Units
PHASE Clock Frequency = MaxPhase Frequency / (I997+1)
Default
0
PHASE Clock Frequency = 9.0346 kHz / 1 = 9.0346 kHz
(with default value of I992)
Remarks
I997, in conjunction with I992, determines the frequency of the PHASE clock on PMAC2
Ultralite. Each cycle of the PHASE clock, a set of MACRO ring information is
transmitted, and any required motor phase commutation and digital current-loop
algorithms are performed for specified motors.