Reference Manual

PMAC 2 Software Reference
376 PMAC Saved Setup Registers
The first table shows the entry values that should be used for ACC-28 boards interfaced to PMAC(1)
Servo ICs. The “m” in the first hex digit refers to the method digit – $1 for un-integrated; $5 for
integrated. The “x” in the second digit is set to $0 for an ACC-28A signed A/D converter, or $8 for an
ACC-28B unsigned A/D converter.
Channel Entry Channel Entry Channel Entry Channel Entry
1 $mxC006 5 $mxC016 9 $mxC026 13 $mx$C036
2 $mxC007 6 $mxC017 10 $mxC027 14 $mx$C037
3 $mxC00E 7 $mxC01E 11 $mxC02E 15 $mx$C03E
4 $mxC00F 8 $mxC01F 12 $mxC02F 16 $mx$C03F
The next table shows the entry values that should be used for ACC-28B boards interfaced to PMAC2
Servo ICs. . The “m” in the first hex digit refers to the method digit – $1 for un-integrated; $5 for
integrated.
Channel Entry Channel Entry Channel Entry Channel Entry
1A $m8C005 5A $m8C025 9A $m8C045 13A $m8C065
1B $m8C006 5B $m8C026 9B $m8C046 13B $m8C066
2A $m8C00D 6A $m8C02D 10A $m8C04D 14A $m8C06D
2B $m8C00E 6B $m8C02E 10B $m8C04E 14B $m8C06E
3A $m8C015 7A $m8C035 11A $m8C055 15A $m8C075
3B $m8C016 7B $m8C036 11B $m8C050 15B $m8C076
4A $m8C01D 8A $m8C03D 12A $m8C05D 16A $m8C07D
4B $m8C01E 8B $m8C03E 12B $m8C05E 16B $m8C07E
Integration Bias: The $5 integrated format requires a second line to specify the bias of the A/D converter.
This bias term is a signed quantity (even for an unsigned A/D converter), with units of 1/256 of the LSB
of the 16-bit A/D converter. This value is subtracted from the reading of the ADC before the integration
occurs.
For example, if there were an offset in a 16-bit ADC of +5 LSBs, this term would be set to 1280. If no
bias is desired, a zero value should be entered here. If the conversion is unsigned, the result after the bias
is not permitted to be less than zero. This term permits reasonable integration, even with an analog offset.
Parallel Feedback Entries ($2, $3, $6, $7) [Modified]: The “parallel feedback” entries read a word from
the address specified in the low 16 bits (bits 0 – 15) of the first line, either a whole word from the single
address specified, or three bytes from three consecutive Y-word addresses starting at the specified
address. The four methods in this class, specified by the first hex digit (bits 20 – 23) are:
• $2: Y-word parallel, no filtering (2-line entry)
• $3: Y-word parallel, with filtering (3-line entry)
• $6: X-word parallel, no filtering (2-line entry)
• $7: X-word parallel, with filtering (3-line entry)
The second hex digit (bits 16 – 19) contains four mode-control bits that govern how the conversion is
done. The four mode-control bits are:
• Bit 16 (digit value 1): Summing control (0 = no summing; 1 = sum with above result) for word-
wide reads only; byte-select bit 0 for byte-wide reads only (depending on bit 18)
• Bit 17 (digit value 2): Reserved for word-wide reads, byte-select bit 1 for byte-wide reads
• Bit 18 (digit value 4): Shift-right/byte-wide-read control (depending on bits 16 and 17)
• Bit 19 (digit value 8): Shift-left control (0 = normal 5-bit left shift; 1 = no or right shift)
These four bits provide multiple combinations for the second hex digit, shown in the following table: