Reference Manual

PMAC 2 Software Reference
PMAC Saved Setup Registers 377
Second
Digit
Conversion Details Second
Digit
Conversion Details
$0 Word-wide source, shift result left 5
bits, no summing
$8 Word-wide source, no shift of result,
no summing
$1 Word-wide source, shift result left 5
bits, summed with above result
$9 Word-wide source, no shift of result,
summed with above result
$2 (Reserved) $A (Reserved)
$3 (Reserved) $B (Reserved)
$4 (Reserved) $C Word-wide source, shift result right 3
bits, no summing
$5 Byte-wide Y source (low byte), shift
result left 5 bits, no summing
$D Byte-wide Y source (low byte), no
shift of result, no summing
$6 Byte-wide Y source (middle byte),
shift result left 5 bits, no summing
$E Byte-wide Y source (middle byte), no
shift of result, no summing
$7 Byte-wide Y source (high byte), shift
result left 5 bits, no summing
$F Byte-wide Y source (high byte), no
shift of result, no summing
Shift control: With the “normal shift”, the LSB of the source register is shifted to bit 5 of the
result register, providing the standard 5 bits of (non-existent here) fractional position data. In this case,
PMAC software regards the LSB as one “count” of position. With the “3-bit right shift”, bit 8 of the
source register is shifted to bit 5 of the result register. This is appropriate for 16-bit data found in the high
16 bits of the source register, such as the old MACRO Type 0 feedback.
With “no shift”, the LSB of the source register ends up in bit 0 of the result register. This mode is used
for one of three reasons:
• The data already comes with 5 bits of fraction, as from a MACRO Station.
• The normal shift limits the maximum velocity too much (V
max
<2
18
LSBs per servo cycle)
• The normal shift limits the position range too much (Range<+
2
47
/Ix08/32 LSBs)
Unless this is done because the data already contains fractional information, the “unshifted” conversion
will mean that the motor position loop will consider 1 LSB of the source to be 1/32 of a count, instead of
1 count.
Word-Wide vs. Byte-Wide: Most types of position data read with the parallel conversion will be
present in a single data word of up to 24 bits. This is “word-wide” data, read with the control bit in bit 18
set to 0, or bit 18 set to 1 and bits 16 and 17 both set to 0.
However, on some interface boards, such as the ACC-14P, the bus interface is only byte wide, so position
data of more than 8 bits is read in bytes of consecutive registers. For this format, the control bit in bit 18
should be set to 1, and the combined value of bits 16 and 17 set to 1, 2, or 3.
If bits 16 and 17 set a combined value of 1, the low bytes (bits 0 – 7) of the selected registers are read. If
bits 16 and 17 set a combined value of 2, the middle bytes (bits 8 – 15) of the selected registers are read.
If bits 16 and 17 set a combined value of 3, the high bytes (bits 16 – 23) of the selected registers are read.
With the byte-wide read, right shifting of the result data is not supported, and summing of the result with
the previous result is not supported. Only Y-registers can be read in byte-wide format, so byte-wide reads
are supported only in methods $2 and $3, not $6 and $7.
In the byte-wide read, the low 16 bits (last 4 hex digits) of the first setup line specify the address of the
first of the three Y-registers to be read. The Y-registers at the next two higher-numbered addresses will