Reference Manual

PMAC 2 Software Reference
PMAC Saved Setup Registers 379
measuring the time between the two. This time is directly proportional to the distance. For this feedback
the “time between last two counts” register is used like an absolute encoder. The following table shows
the first line of the parallel feedback entry for each channel’s timer register:
MLDT Timer Entries
Channel Entry Channel Entry Channel Entry Channel Entry
1 $30C000 5 $30C020 9 $30C040 13 $30C060
2 $30C008 6 $30C028 10 $30C048 14 $30C068
3 $30C010 7 $30C030 11 $30C050 15 $30C070
4 $30C018 8 $30C038 12 $30C058 16 $30C078
The second line in an MLDT entry should be $07FFFFF to specify the use of the low 19 bits.
The third line in an MLDT entry should contain a number slightly greater than the maximum velocity
ever expected, expressed as timer increments per servo cycle. An increment of the 120 MHz timer
represents about 0.024mm (0.0009 in) on a typical MLDT device. This value represents the maximum
change in position reading that will be passed through the conversion table in a single servo cycle, and it
provides an important protection against missing or spurious echo pulses.
Word-Wide Parallel Feedback: The ACC-14D and 14V boards are often used to connect parallel data
from an absolute encoder or interferometer. The following table shows the entry first lines for the
registers on these boards. The latched input registers on ACC-14D/V boards are mapped into Y-registers
and filtering is usually desired, so a $3 method digit is used. In most cases, the normal shift is applied,
making the second digit $0, but if the feedback has very high resolution, as can happen with an
interferometer, the second digit should be set to $8 to disable shifting.
ACC-14D/V Port Entries
ACC 14 # Port Entry ACC 14 # Port Entry
1 A $3xFFD0 4 A $3xFFE8
1 B $3xFFD1 4 B $3xFFE9
2 A $3xFFD8 5 A $3xFFF0
2 B $3xFFD9 5 B $3xFFF1
3 A $3xFFE0 6 A $3xFFF8
3 B $3xFFE1 6 B $3xFFF9
x = 0: normal shift; x = 8: no shift
Byte-Wide Parallel Feedback: The ACC-14P is a PCI-format board that can be used to connect parallel
data from an absolute encoder or interferometer. The following table shows the entry first lines for the
registers on these boards. The latched input registers on ACC-14D/V boards are mapped into Y-registers
and filtering is usually desired, so a $3 method digit is used.
The data is byte-wide, so bit 18 (value of 4 in the second digit) is set to 1. Ports A and B occupy the low
bytes of each word, so bits 16 and 17 get a combined value of 1, making the second hex digit $5. Ports C
and D occupy the middle bytes of each word, so bits 16 and 17 get a combined value of 2, making the
second hex digit $6. If no shifting of the result data is desired, bit 19 (value of 8 in this digit) is also set to
1, making the second hex digit $D or $E
Ports A and C on these boards start in the board’s base address; Ports B and D start in {Base+3}.