Reference Manual

PMAC 2 Software Reference
394 PMAC Saved Setup Registers
Bit 18 of a hardware channel’s control word permits the enabling of a special hardware 1/T sub-count
estimation for the channel in the PMAC2 DSPGATE1 Servo ASIC. (This requires revision “D” or newer
of the DSPGATE1 IC, which started shipping in 2002.)
If bit 18 is set to 1, the ASIC will automatically compute 12 bits of timer-based estimated sub-count data
every SCLK encoder sample clock cycle (default 9.83 MHz). This sub-count position data is then
available to enhance the resolution of the hardware capture and compare functions.
When bit 18 is set to the default value of 0, the hardware 1/T functionality is disabled.
The addresses for the control word of each channel are:
Channel Control
Word
Address
Channel Control
Word
Address
Channel Control
Word
Address
Channel Control
Word
Address
1 X:$C005 3 X:$C015 5 X:$C025 7 X:$C035
2 X:$C00D 4 X:$C01D 6 X:$C02D 8 X:$C03D
When the hardware 1/T functionality is enabled by setting bit 18 to 1, the registers needed for the
traditional software 1/T in the encoder conversion table are no longer accessible. At these addresses (the
first two Y-registers for the channel in the ASIC) are instead four 12-bit sub-registers for sub-count
capture and compare data.
The hardware 1/T functionality is mainly intended for use with the ACC-51x high-resolution interpolator
boards for sinusoidal encoders. That board produces 10 bits of fractional count resolution for servo
feedback with its A/D converters, but that fractional data cannot be used for hardware capture or compare
functions between servo cycles.
X:$C014, X:$C034 Servo IC m ADC Strobe Word {PMAC2 only}
Range: $000000 - $FFFFFF
Units: Serial Data Stream (MSB first, starting on rising edge of phase clock)
Default: $FFFFFE
X:$C014 and X:$C034 control the ADC strobe signal for Servo IC machine interface channels 1 – 4 and
5 – 8, respectively. The 24-bit word set by these registers is shifted out serially on the ADC_STROB
lines, MSB first, one bit per ADC_CLK cycle starting on the rising edge of the phase clock.
In revisions “D” and newer of the DSPGATE1 Servo IC (beginning shipments in 2002), bit 0 (the LSB)
of X:$C014 and X:$C034 is a control bit that determines whether the Servo IC will expect “header”
information on the return data streams that precedes the numerical data from the ADCs. If bit 0 is 0, no
header information is expected, and the low output from this bit is held until the next rising edge of the
phase clock. This setting must be used on all earlier revisions of the DSPGATE1 Servo IC.
In revisions “D” and newer, if bit 0 of X:$C014 or X:$C034 is 1, up to 4 bits of header information can
be accepted on the returned serial data streams from the ADCs (as with the ADCs in Delta Tau’s Geo
power block amplifiers). These bits are “rolled over” and end up in bits 0 – 3 of the ADC register in the
Servo IC, and the numerical data ends up with its MSB in bit 23 of the ADC register. If fewer than 4
header bits are expected, the beginning of the strobe word should be delayed by setting the first bit(s) of
the register to 0. Specifically, if (4 – n) header bits are expected, the first n bits of the register should be
set to 0. In this setting, the ADC_STROB output is taken low and held low after bit 0 is shifted out.
The first bit that is a 1 creates a rising edge on the ADC_STROB output that is used typically as a start-
convert signal. Some A/D converters just need this rising edge for the conversion; others need the signal
to stay high all of the way through the conversion. Intermediate bits of the ADC_STROB output can be
used to transmit other information in some applications.