Reference Manual

PMAC 2 Software Reference
PMAC I/0 and Memory Map 429
X:$C08F
DSPGATE2 clock control register
(Bits 0-11 comprise I993)
0-2 Handwheel SCLK* Frequency Control n
(f=39.3216MHz / 2
n
, n=0-7)
3-5 JHW/PD PFM Clock Frequency Control n
(f=39.3216MHz / 2
n
, n=0-7)
6-8 Not used
9-11 ADC Clock* Frequency Control n (f=39.3216MHz /
2
n
, n=0-7)
12 Phase Clock Direction (0=output, 1=input. This must be
1)
13 Servo Clock Direction (0=output, 1=input. This must be
1)
14-15 Not used (report as zero)
16-19 (I997 – normally used on PMAC2 UltraLite only) Phase
Clock* Frequency Control n (f=MAXPHASE* / [n+1],
n=0-15)
20-23 (I998 – normally used on PMAC2 UltraLite only) Servo
Clock* Frequency Control n (f=PHASE* / [n+1], n=0-
15)
Chan #
1* 2*
Hex
[$C090] [$C098]
Decimal
49296 49304
Y:$C09x
Handwheel n Time between last two encoder counts
(SCLK cycles)
Bits
X:$C09x
Supplementary Channel n* (Handwheel n) Status Word
0-2 Captured Hall Effect Device (UVW) State
3-7 Not used (reports as zero)
8 Encoder Count Error (0 on counter reset, 1 on illegal
transition)
9 Position Compare (EQUn*) output value
10 Position-Captured-On-Gated-Index Flag (=0 on read of
captured position register, =1 on trigger capture)
11 Position-Captured Flag (on any trigger) (=0 on read of
captured position register, =1 on trigger capture)
12 Handwheel 1 Channel A (HWAn) Input Value
13 Handwheel 1 Channel B (HWBn) Input Value
14 Handwheel 1 Channel C (Index, HWCn) Input Value
(ungated)
15 Amplifier Fault (FAULTn*) Input Value
16 Home Flag (HMFLn*) Input Value
17 Positive End Limit (PLIMn*) Input Value
18 Negative End Limit (MLIMn*) Input Value
19 User Flag (USERn*) Input Value
20 FlagWn* Input Value
21 FlagVn* Input Value
22 FlagUn* Input Value
23 FlagTn* Input Value