User's Manual

Turbo PMAC2 VME Ultralite
2 Introduction
Option 1: Additional MACRO Interface Ics
The basic board has one MACRO interface IC and space for three more. Variations of Option 1 fill these
spaces as follows:
• Option 1A provides the first additional MACRO interface IC (two total) for 16 additional MACRO
nodes, eight additional servo nodes and eight additional I/O nodes (32 nodes total, 16 servo and 16
I/O). The key component on the board is U23.
• Option 1B provides the second additional MACRO interface IC (three total) for 16 additional
MACRO nodes, eight additional servo nodes and eight additional I/O nodes (48 nodes total, 24 servo
and 24 I/O). The key component on the board is U24. Option 1A is a pre-requisite.
• Option 1C provides the third additional MACRO interface IC (four total) for 16 additional MACRO
nodes, eight additional servo nodes and eight additional I/O nodes (64 nodes total, 32 servo and 32
I/O). The key component on the board is U25. Options 1A and 1B are pre-requisites.
Option 2: Dual-Ported RAM
Dual-ported RAM provides a high-speed communications path for bus communications with the host
computer through a bank of shared memory. DPRAM is advised if more than about 100 data items per
second are to be passed between the controller and the host computer in either direction. Option 2
provides a 32k x 16 bank of dual-ported RAM. The key component on the board is U191.
Option 5: CPU and Memory Configurations
The various versions of Option 5 provide different CPU speeds and main memory sizes. Only one Option
5xx may be selected for the board.
The CPU is a DSP563xx IC as component U56. The CPU is available in several speed options: 80 MHz
CPU is a DSP56303 (Option 5Cx), 100 MHz CPU is a DSP56309 (Option 5Dx), and 160 MHz CPU is a
DSP56311 (Option 5Ex). The maximum frequency of operation is indicated with a sticker on the CPU in
U56.
The compiled/assembled-program memory SRAM ICs are located in U40, U43, and U47. These ICs
form the active memory for the firmware, compiled PLCs, and user-written phase/servo algorithms.
These can be 128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger
512k x 8 ICs (for a 512k x 24 bank), fitting in the full footprint.
The user-data memory SRAM ICs are located in U39, U42, and U46. These ICs form the active memory
for user motion programs, uncompiled PLC programs, and user tables and buffers. These can be 128k x 8
ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger 512k x 8 ICs (for a
512k x 24 bank), fitting in the full footprint.
The flash memory IC is located in U45. This IC forms the non-volatile memory for the board’s firmware,
the user setup variables, and for user programs, tables, and buffers. It can be 1M x 8, 2M x 8, or 4M x 8
in capacity.
• Option 5C0: Default CPU speed and memory configuration: 80MHz DSP56303 CPU (8Kx24
internal memory), 128Kx24 SRAM compiled/assembled program memory, 128Kx24 SRAM user
data memory, 1Mx8 flash memory.
• Option 5C3: 80MHz DSP56303 CPU (8Kx24 internal memory), expanded 512Kx24 SRAM
compiled/assembled program memory, expanded 512Kx24 RAM user data memory, 4Mx8 flash
memory.
• Option 5D0: 100MHz DSP56309 CPU (34Kx24 internal memory), 128Kx24 SRAM
compiled/assembled program memory, 128Kx24 SRAM user data memory, 1Mx8 flash memory.