Specifications

ADC12EU050
www.ti.com SNAS444I –JANUARY 2008–REVISED APRIL 2013
Coefficent a[2:0] Coefficent b[2:0] Digital Gain (dB) Equivalent full scale
input range (V
PP
)
010 010 4.16 1.30
010 001 3.95 1.33
010 000 3.74 1.37
010 111 3.52 1.40
010 110 3.29 1.44
001 001 3.06 1.48
001 000 2.82 1.52
001 111 2.58 1.56 IOR Mode default setting
001 110 2.33 1.61
000 001 2.07 1.65
000 000 1.80 1.71
000 111 1.53 1.76
000 110 1.24 1.82
111 001 0.95 1.88
111 000 0.64 1.95
111 111 0.33 2.02
111 110 000 2.10 ADC mode default setting
110 001 -0.34 2.18
110 000 -0.70 2.28
110 111 -1.07 2.38
110 110 -1.45 2.48
Decimator Control Register
• Address: 16h
• Attributes: Write Only
• Register 17h reads back contents of register 16h
b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] HEX
Description Reserved EQON DFS MSB TSEL[1:0]
Default 0 0 0 0 0 0 0 0 00 h
Bit Description
7:5 Reserved. Write as zero for future compatibility.
4 EQON: Equalizer Enable. This bit is used to enable or disable the digital equalizer. The equalizer can be
switched on in order to reduce the group delay of the output data, at the cost of increased power.
0 Equalizer disabled
1 Equalizer enabled
3 DFS: Data Format Select. Selects the format, either Offset Binary or Twos Complement of the output data
0 2s Complement
1 Offset Binary
2 MSB: Select the bit order of the LVDS output data stream
0 LSB first
1 MSB first
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