User Guide

47
AVR-5805/AVC-A1XV
103 P10 DAMSS O C - - - Z FPGA control for DAC
104 P07/AN07 DAPLDDATAS O C - - - Z FPGA control for DAC
105 P06/AN06 DAPLDCLKS O C - - - Z FPGA control for DAC
106 P05/AN05 DAPLDSTBS O C - - - Z FPGA control for DAC
107 P04/AN04 NC O C - - - Z Not used
108 P03/AN03 INT2 I - E ↓ &L - Ed Z DIR2 control pin (LC89057W-E)
109 P02/AN02 INT3 I - E ↓ &L - Ed Z DIR3 control pin (LC89057W-E)
110 P01/AN01 INT4 I - E ↓ &L - Ed Z DIR4 control pin (LC89057W-E)
111 P00/AN00 INT5 I - E ↓ &L - Ed Z DIR5 control pin (LC89057W-E)
112 P117 INT6 I - E ↓ &L - Eu Z DIR6 control pin (LC89057W-E) ( ※ "Z"set: Operated from ZONE μcom)
113 P116 INT7 I - E ↓ &L - Eu Z DIR7 control pin (LC89057W-E) ( ※ "Z"set: Operated from ZONE μcom)
114 P115 INT8 I - E ↓ &L - Eu Z DIR8 control pin (LC89057W-E) ( ※ "Z"set: Operated from ZONE μcom)
115 P114 NC Ｉ - - - - Z Not used
116 P113 DSPCSS O C - - Eu Z PLD control for DSP chip select
117 P112 DSPA0S O C - - - Z PLD control for DSP （3-bit address for target selection of RST/CS)
118 P111 DSPA1S O C - - - Z PLD control for DSP （3-bit address for target selection of RST/CS)
119 P110 DSPA2S O C - - - Z PLD control for DSP （3-bit address for target selection of RST/CS)
120 P107/AN7 DSPREQ1S I - - - - Z PLD control for DSP(use with DSP READY)
121 P106/AN6 DSPREQ2S I - - - - Z PLD control for DSP(use with DSP READY)
122 P105/AN5 DSPREQ3S I - - - - Z PLD control for DSP(use with DSP READY)
123 P104/AN4 NC I - - - - Z Not used
124 P103/AN3 NC I - - - - Z Not used
125 P102/AN2 NC I - - - - Z Not used
126 P101/AN1 DSPROMRSTS O C - - Ed Z PLD control for DSP memory reset（Reset: L)
127 AVSS AVSS - - - - - - AD GND
128 P100/AN0 DSPRSTS O C - - Ed Z PLD control for DSP reset（Reset: L)
Pin Pin Name Symbol I/O Type Det
Op
(Int.)
Op
(Ext.)
Res FUNCTION