Parallax P2 Edge Module - Datasheet
Table Of Contents
- FEATURES
- HARDWARE
- Pin Descriptions
- Hardware Connections
- Minimal Connections
- External Crystal
- Reset Switch
- SPI Flash Boot Memory
- MicroSD Boot Memory
- Dual Boot Memory
- OPERATION
- SYSTEM ORGANIZATION
- Cogs
- Cog RAM
- Register RAM
- Lookup RAM
- Execution
- Hub
- Hub RAM
- Cog-to-Hub RAM Interface
- System Clock
- CORDIC Solver
- Smart I/O Pins
- Pin Modes
- I/O Pin Circuit
- Equivalent Schematics
- Smart Modes
- PASM2 LANGUAGE IN BRIEF
- Math and Logic
- Pin & Smart Pin
- Branch
- Hub Control, FIFO, & RAM
- Event
- Interrupt
- Register Indirection
- CORDIC Solver
- Color Space Converter and Pixel Mixer
- Lookup Table, Streamer, and Misc
- SYSTEM CHARACTERISTICS
- Absolute Maximum Electrical Ratings
- DC Characteristics
- AC Characteristics
- PACKAGING
- CHANGE LOG
- PARALLAX INCORPORATED
through their Lookup RAMs. Use the SETLUTS instruction to enable/disable this feature and SETSE1..4 to
facilitate handshaking if necessary. Note that this adjacent cog access is implemented on the Lookup RAM's 2nd
port, which is also used by the streamer in DDS/LUT modes; these are not intended to used simultaneously.
Execution
Cogs employ a five-stage pipelined execution architecture. When the execution pipeline is full, each PASM2
instruction effectively takes as little as two clock cycles to execute. If an instruction stalls for additional clock
cycles, all following instructions in the pipeline are also stalled. Any instruction that is conditionally cancelled will
still move through the pipeline without stalling or executing. Branch instructions cause the pipeline to be flushed,
so the first instruction following the branch will take at least five clock cycles.
Cogs use 20-bit addresses for their program counters (PC); the upper bit is a "don't care" bit - this affords an
execution space of up to 512 KB. Depending on the value of a cog's PC, an instruction will be fetched from either
its Register RAM, its Lookup RAM, or the Hub RAM.
PASM2 Execution Regions
PC Address
Instruction Source
Memory Width
PC Increment
$00000..$001FF
Cog Register RAM
32 bits
1
$00200..$003FF
Cog Lookup RAM
32 bits
1
$00400..$7FFFF
Hub RAM
8 bits
4
Register Execution
When the PC is in the range of $00000 to $001FF, the cog fetches instructions from Cog Register RAM. This is
referred to as "cog execution." There are no special considerations when branching to a cog register address.
Lookup Execution
When the PC is in the range of $00200 to $003FF, the cog fetches instructions from Cog Lookup RAM. This is
referred to as "lut execution." There are no special considerations when branching to a cog lookup address.
Hub Execution
When the PC is in the range of $00400 to $7FFFF, the cog fetches instructions from Hub RAM. This is referred to
as "hub execution mode." Special considerations are involved with hub execution.
1. The PC rolling beyond $003FF will not initiate hub execution (it will just wrap back to $00000); a branch
must occur to get from register or lookup execution to hub execution.
2. Branching to a hub address takes a minimum of 13 clock cycles. If the instruction being branched to is
not long-aligned, one additional clock cycle is required.
3. When executing from Hub RAM, the cog employs the FIFO hardware to spool up instructions so that a
stream of instructions will be available for continuous execution. This means the FIFO cannot be used for
anything else. So, during hub execution these instructions cannot be used:
RDFAST / WRFAST / FBLOCK
RFBYTE / RFWORD / RFLONG / RFVAR / RFVARS
WFBYTE / WFWORD / WFLONG
XINIT / XZERO / XCONT - when the streamer mode engages the FIFO
It is not possible to execute code from hub addresses $00000 through $003FF, as the cog will instead read
instructions from the cog's Register RAM or Lookup RAM as indicated above.
Copyright © Parallax Inc. 2021/05/27 ▪ Parallax Propeller 2 (P2X8C4M64P) Datasheet ▪ Page 13