Parallax P2 Edge Module - Datasheet
Table Of Contents
- FEATURES
- HARDWARE
- Pin Descriptions
- Hardware Connections
- Minimal Connections
- External Crystal
- Reset Switch
- SPI Flash Boot Memory
- MicroSD Boot Memory
- Dual Boot Memory
- OPERATION
- SYSTEM ORGANIZATION
- Cogs
- Cog RAM
- Register RAM
- Lookup RAM
- Execution
- Hub
- Hub RAM
- Cog-to-Hub RAM Interface
- System Clock
- CORDIC Solver
- Smart I/O Pins
- Pin Modes
- I/O Pin Circuit
- Equivalent Schematics
- Smart Modes
- PASM2 LANGUAGE IN BRIEF
- Math and Logic
- Pin & Smart Pin
- Branch
- Hub Control, FIFO, & RAM
- Event
- Interrupt
- Register Indirection
- CORDIC Solver
- Color Space Converter and Pixel Mixer
- Lookup Table, Streamer, and Misc
- SYSTEM CHARACTERISTICS
- Absolute Maximum Electrical Ratings
- DC Characteristics
- AC Characteristics
- PACKAGING
- CHANGE LOG
- PARALLAX INCORPORATED
CHANGE LOG
Date
Notes
2021-05-05
First public release.
2021-05-27
Added Cog RAM, Locks, CORDIC Solver, and Smart I/O Pins sections.Updated all Hardware Connection
diagrams.Corrected Hub RAM size typo and clarified address type in Propeller 2 (P2X8C4M64P) RAM
Memory Configuration table.
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Purchase of the P2X8C4M64P does not include any license to emulate any other device nor to communicate
via any specific proprietary protocol; P2X8C4M64P connectivity objects and code examples provided or
referenced by Parallax, Inc. are NOT licensed and are provided for research and development purposes only;
end users must seek permission to use licensed protocols for their applications and products from the protocol
license holders.
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Copyright © Parallax Inc. 2021/05/27 ▪ Parallax Propeller 2 (P2X8C4M64P) Datasheet ▪ Page 47