User's Manual
Table Of Contents
- About the Modules
- What’s on the Module?
- About the Development Board
- Basic description
- Switches and buttons
- I2C and SPI header connectors
- Serial port connectors
- VGA connector / External LCD clock
- Development board SO-DIMM connector, P15
- Application-specific expansion headers - P16 and P17
- LCD application board header, P18
- USB Device application header, P32
- Digital I/O, P19
- Power over Ethernet (PoE) connectors
- Through-hole prototyping (wrap-field) area, P3 and P4
- Development board LEDs
- Current Measurement Option (CMO)
- Power jack, P12
- Test points
- Factory default interface configuration for development board
- LCD and USB Configuration
- Module Specifications
- Mechanical dimensions
- Environmental information
- Network interface
- Power requirements
- Real-time clock
- I2C signals
- USB interface
- Module reset
- Module / SO-DIMM signal characteristics
- Electrical characteristics
- DC electrical characteristics
- USB internal PHY DC electrical inputs and outputs
- Antenna information
- Antenna specifications - 2 dBi Dipole
- Antenna specifications - 5 dBi Dipole
- Antenna specifications - 2 dBi PCB mount
- FCC RF radiation exposure statement
- Safety statements
- Dimensions and PCB Layouts
- Certifications
LCD AND USB CONFIGURATION
Sample applications
62 ConnectCore 9c/Wi-9C Hardware Reference, Rev. B 01/2007
4
The ConnectCore 9C/Wi-9C development board has a 48MHz external oscillator and
resulting LCD clock of 24MHz. 16 bits of color requires 48 MBps for the display.
Default LCD
controller
The default LCD controller configuration supported by the NS9360 is 640 x 480, with
8 bits for color. The bandwidth is guaranteed; the designer does not need to be
concerned with bandwidth use. Higher resolutions are possible but require care in
their setup and design.
Formula The ConnectCore 9C/Wi-9C module operates at 155 MHz system bus speed. This
speed grade results in 310 MBps bus bandwidth, as the bus is 4 bytes wide. For
bandwidth planning, this maximum bandwidth must be reduced to account for
overhead and read/write switching. The effective bandwidth is 1/2 of the system
bandwidth; that is, 155 MBps. This value is predicted as the worst case for the
ConnectCore 9C/Wi-9C. The architecture allocates half of the system bandwidth to
the module. The remaining four bus master peripherals (Ethernet TX, Ethernet RX,
peripheral bus bridge, and LCD controller) share the other half of the bandwidth.
The bandwidth assignment of these peripherals is programmable.
Use this formula to estimate the amount of bandwidth available for your LCD
display:
CPU bandwidth = 77.5 MBps
All other peripherals (including LCD) = 77.5 MBps
Example 1: 18-bit
VGA
The 18-bit TFT display transfers 16 bits per pixel and generates the last two bits
inside the LCD controller. This display packs two-color RGB pixels into a single 4-
byte word.
The 18-bit VGA display (640 x 480), refreshing 60 times per second, requires 37
MBps:
2 x 640 x 480 x 60 = 37 MBps
40.5 MBps are left to all other peripherals. If the LCD refresh frequency increases to
70 Hz, the required bandwidth increases to 43 MBps.
Note:
The module LCD controller supports 18-bit VGA displays in most applications.
Supported TFT
displays
Display type Refresh
frequency in Hz
BW required for
display in MBps
Display in MBps
BW left to other
peripherals in MBps
18b VGA (640 x 480) 50 31 46.5
60 37 40.5
70 43 34.5