User's Manual
Table Of Contents
- About the Modules
- What’s on the Module?
- About the Development Board
- Basic description
- Switches and buttons
- I2C and SPI header connectors
- Serial port connectors
- VGA connector / External LCD clock
- Development board SO-DIMM connector, P15
- Application-specific expansion headers - P16 and P17
- LCD application board header, P18
- USB Device application header, P32
- Digital I/O, P19
- Power over Ethernet (PoE) connectors
- Through-hole prototyping (wrap-field) area, P3 and P4
- Development board LEDs
- Current Measurement Option (CMO)
- Power jack, P12
- Test points
- Factory default interface configuration for development board
- LCD and USB Configuration
- Module Specifications
- Mechanical dimensions
- Environmental information
- Network interface
- Power requirements
- Real-time clock
- I2C signals
- USB interface
- Module reset
- Module / SO-DIMM signal characteristics
- Electrical characteristics
- DC electrical characteristics
- USB internal PHY DC electrical inputs and outputs
- Antenna information
- Antenna specifications - 2 dBi Dipole
- Antenna specifications - 5 dBi Dipole
- Antenna specifications - 2 dBi PCB mount
- FCC RF radiation exposure statement
- Safety statements
- Dimensions and PCB Layouts
- Certifications
MODULE SPECIFICATIONS
Module / SO-DIMM signal characteristics
70 ConnectCore 9C/Wi-9C Hardware Reference, Rev. B 01/2007
A
The ADM811S asserts the hard reset signal, causing the entire system to go
into reset. Manual reset input is wired to ADM811S from JTAG header P2.
The minimum pulse width for reset signal is 10μs.
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Module / SO-DIMM signal characteristics
Note:
All signal directions are referenced as into or out of the ConnectCore Wi-9C
module.
I/O class details
Note:
For internal pullup calculations, see the NS9360 Hardware Reference
(available through the Jump Start Kit).
Signal
characteristics
I/O class Class description Minimum high-level
input current source
Minimum low-level
input current sink
Class 1 Standard LVTTL 10 μA10 μA
Class 2 LVTTL + internal pullup 10 μA210 μA
Class 3 LVTTL + internal pullup+2.4k
external pulldown (strapping)
840 μA210 μA
Class 4 3.3V LVC BUS HOLD LVTTL
I/O
75 μA75 μA
Pin SIgnal name Internal
U/D
OD
(mA)
I/O Description I/O
class
Notes / Bootstrapping (BS)
1 GND
2 GND
3 +3.3V I
4 +3.3V I
5 +3.3V I
6 +3.3V I
7 WAKEUP#
PWRDWN#
I
I
Wi-9C: Wakeup after
sleep mode
CC9C: Power down
Reserved
8 UBUFFENR# 24 O User buffer enable Holds user buffers off during
powerup/down and until boot is done
9 DATA_0 12 BI Data bus signal 4