Reference Manual

19 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Chapter 1
low battery state. If this feature is not used, the pin has to be left open, because a
10k pull up resistor is provided at the module.
Analog voltage AVCC and AGND, e.g. for a touch screen, are also provided on the
module system connector.
For the power control logic, the S3C2443 has various power management schemes
to keep optimal power consumption for a given task. These schemes are related to
PLL, clock control logics (ARMCLK, HCLK, and PCLK) and wakeup signals.
 ARMCLK is used for ARM920T core.
 HCLK is the reference clock for internal AHB bus and peripherals such as the
memory controller, the interrupt controller, LCD controller, the DMA, USB host
block, System Controller, Power down controller and etc.
 PCLK is used for internal APB bus and peripherals such as WDT, IIS, I2C, PWM
timer, ADC, UART, GPIO, RTC and SPI etc.
The following figure shows the clock distribution:
Power
management
The power management block in the S3C2443 can activate four modes: NORMAL,
STOP, IDLE, and SLEEP. These are described below.