Reference Manual

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 To enter sleep mode by BATT_FLT, BATF_CFG bits of PWRCFG register must be
configured.
 Do not exit from sleep mode when BATT_FLT is LOW; SLEEP_CFG bit of PWRCFG
register must be configured.
A Battery Fault Signal (BATT_FLT#) is provided at the CPU to recognize the battery
state of the battery at the base board, which powers the module. Therefore this pin
is routed to the system connector. At the base board a comparator has to supervise
the battery state and the output of the comparator delivers the BATT_FLT# signal.
The figure below shows the power management state diagram:
Reset There are 3 reset signals defined, which are routed to the system connector:
 a reset input to the module (RSTIN#)
 an output of the reset controller from the module (PWRGOOD)
 a reset output from the CPU (RSTOUT#)
Mode before wake-up PLL on/off after wake-up SYSCLK after wake-up
and before the lock time
SYSCLK after the lock
time by internal logic
IDLE Unchanged PLL output PLL output
STOP PLL state ahead of entering STOP
mode (PLL ON or not)
PLL reference clock SYSCLK ahead of entering
STOP mode (PLL output or
not)
SLEEP Off PLL reference clock PLL reference (input) clock
Wake-up source
Wake-up source
Reset or restricted
wake-up events