Reference Manual

www.digiembedded.com 24
 SFR I/F: Supports Little Endian Mode, Byte/half word/word access to Data and
ECC Data register, and Word access to other registers.
 Steppingstone I/F: Supports Little/Big Endian, Byte/half word/word access.
 The Steppingstone 4-KB internal SRAM buffer can be used for another purpose
after NAND flash booting.
The write protect pin of the Flash device is routed to the hardware configuration
pin of the system connector FWP#. The device can be write protected at the base
board by connecting this pin to GND. At the module, a pull-up resistor is equipped.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration pins - CPU module
There are eight configuration pins provided on the system connector. Four of them
are provided as hardware configuration pins, and the other four can be used as
software configuration pins. A 10k pull up resistor is provided on each signal line of
the configuration pins.
The following pins on the connector are defined as hardware configuration pins:
The following port pins are defined as software configuration pins:
The signal DEBUGEN# (CONF0) from the base board to the module is necessary to
allow switching a connection on and off between the system reset and the JTAG
reset.
Signal Description
DEBUGEN# Debug enable
FWP# Write protect of internal flash
CONF2 Hardware configuration 2 (not yet used)
CONF3 Hardware configuration 3 (not yet used)
Signal Port Pin Description
CONF4 GPF2 Software configuration 0
CONF5 GPF3 Software configuration 1
CONF6 GPF4 Software configuration 2
CONF7 GPF5 Software configuration 3
Signal State Description
DEBUGEN# High Switch is on, TRST# and PWRGOOD are connected (default)
DEBUGEN# Low Switch is off, TRST# and PWRGOOD are disconnected