Reference Manual

45 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Chapter 1
(TCMPBn) has an initial value which is loaded into the compare register to be
compared with the down-counter value. This double buffering feature of TCNTBn and
TCMPBn makes the timer generate a stable output when the frequency and duty ratio
are changed.
Each timer has its own 16-bit down counter, which is driven by the timer clock. When
the down counter reaches zero, the timer interrupt request is generated to inform
the CPU that the timer operation has been completed. When the timer counter
reaches zero, the value of corresponding TCNTBn is automatically loaded into the
down counter to continue the next operation. However, if the timer stops, for
example, by clearing the timer enable bit of TCONn during the timer running mode,
the value of TCNTBn will not be reloaded into the counter.
The value of TCMPBn is used for pulse width modulation (PWM). The timer control
logic changes the output level when the down-counter value matches the value of the
compare register in the timer control logic. Therefore, the compare register
determines the turn-on time (or turn-off time) of a PWM output.
Features:
 Five 16-bit timers
 Two 8-bit prescalers & Two 4-bit divider
 Programmable duty control of output waveform (PWM)
 Auto reload mode or one-shot pulse mode
 Dead-zone generator
All of the Timer outputs are connected to the system connector.
Clock output At the global pins of the system connector there is a clock signal available
(BCLKOUT0), which is buffered by a clock buffer and can be chosen to be either MPLL
CLK, EPLL CLK, FCLK, HCLK, PCLK or DCLK. The source of this clock signal is the
CLKOUT0 port at the CPU, which can be programmed to different clocks, by the
CLKSEL0 register.
The following table shows the bits [6:4] of the CLKSEL0 register:
CF/ATA The single-slot CF controller consists of 2 parts - PC card controller & ATA controller.
They are multiplexing from or to PAD signals. Users can select either PC card or
True-IDE mode operation. Default mode is PC card mode. The CF controller has a
top level SFR with card power enable bit, output port enable bit & mode select
(True-IDE or PC card) bit.
CLKSELO [6.4] 000 001 010 011 100 101 11x
CLKOUT0 MPLL CLK EPLL CLK FCLK HCLK PCLK DCLK0 Reserved