NS9215 Hardware Reference 90000847_C Release date: 10 April 2008
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Contents ..................................................................... C h a p t e r 1 : P i n o u t ( 2 6 5 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 The Legend .............................................................................. 27 Memory bus interface......................................................................... 28 Ethernet interface MAC.......................................................................
GPIO Configuration Register #15 ..................................................... 63 GPIO Configuration Register #16 ..................................................... 64 GPIO Configuration Register #17 ..................................................... 64 GPIO Configuration Register #18 ..................................................... 65 GPIO Configuration Register #19 ..................................................... 65 GPIO Configuration Register #20 ...................................
..... ICache and DCache behavior ..........................................................90 R2: Translation Table Base register.........................................................91 Register format..........................................................................91 R3:Domain Access Control register..........................................................91 Register format..........................................................................91 Access permissions and instructions .........
Access instructions ....................................................................103 Register format ........................................................................103 Performing a fast context switch ...................................................103 Context ID register ....................................................................104 Access instructions ....................................................................104 Register format ........................................
..... MMU faults and CPU aborts................................................................. 119 Alignment fault checking ............................................................ 119 Fault Address and Fault Status registers .......................................... 119 Priority encoding table............................................................... 120 Fault Address register (FAR)......................................................... 120 FAR values for multi-word transfers ................
High speed bus system ................................................................138 High-speed bus arbiters...............................................................138 How the bus arbiter works ...........................................................138 Ownership...............................................................................139 Locked bus sequence..................................................................139 Relinquishing the bus ........................................
..... AHB Error Detect Status 2 .................................................................. 160 AHB Error Monitoring Configuration register ............................................ 161 Timer Master Control register ............................................................. 162 Timer 0–4 Control registers................................................................. 164 Timer 5 Control register ....................................................................
Low-power SDRAM partial array refresh ...........................................204 Memory map...................................................................................205 Power-on reset memory map ........................................................205 Chip select 1 memory configuration ................................................205 Example: Boot from flash, SRAM mapped after boot ............................205 Example: Boot from flash, SDRAM remapped after boot ........................
..... 222 Memory banks constructed from 16-or 32-bit memory devices................ 223 Dynamic memory controller................................................................ 225 Write protection ...................................................................... 225 Access sequencing and memory width............................................. 225 SDRAM Initialization .........................................................................
Static Memory Write Delay 0–3 registers..................................................257 StaticMemory Turn Round Delay 0–3 registers ...........................................258 C h a p t e r 6 : E t h e r n e t C o m m u n i c a t i o n M o d u l e . . . . . . . . . . . . . . . . . . . . . . 261 Features .................................................................................261 Common acronyms ....................................................................
..... Writing to other registers............................................................ 276 Ethernet Control and Status registers .................................................... 277 Register address filter................................................................ 277 Ethernet General Control Register #1 .................................................... 279 Ethernet General Control Register #2 .................................................... 282 Ethernet General Status register .......
Transmit statistics counters address map .........................................307 Transmit byte counter (A060 06E0) .................................................307 Transmit packet counter (A060 06E4) ..............................................308 Transmit multicast packet counter (A060 06E8) ..................................308 Transmit broadcast packet counter (A060 06EC) .................................308 Transmit deferral packet counter (A060 06F4) ...................................
..... Multicast Low Address Filter Register #6 .......................................... 328 Multicast Low Address Filter Register #7 .......................................... 328 Multicast High Address Filter Register #0 ......................................... 328 Multicast High Address Filter Register #1 ......................................... 328 Multicast High Address Filter Register #2 ......................................... 328 Multicast High Address Filter Register #3 ........................
Buffer length ...........................................................................340 Destination address [pointer] ........................................................340 Status ....................................................................................341 Wrap (W) bit............................................................................341 Interrupt (I) bit.........................................................................341 Last (L) bit ...................................
..... Last (L) bit ............................................................................. 358 Full (F) bit.............................................................................. 358 Decryption .................................................................................... 359 ECB processing ............................................................................... 359 Processing flow diagram .............................................................
[Module] DMA RX Control....................................................................375 [Module] DMA RX Buffer Descriptor Pointer ..............................................376 [Module] RX Interrupt Configuration register ............................................377 [Module] Direct Mode RX Status FIFO......................................................378 [Module] Direct Mode RX Data FIFO .......................................................379 [Module] DMA TX Control.......................
..... UART UART UART UART UART FIFO Control register................................................................. 409 Line Control register ................................................................. 409 Modem Control register ............................................................. 411 Line Status register .................................................................. 411 Modem Status register ...............................................................
SPI module structure ..................................................................434 SPI controller..................................................................................434 Simple parallel/serial data conversion .............................................434 Full duplex operation .................................................................434 SPI clocking modes ...........................................................................435 Timing modes ...............................
..... Register bit assignment .............................................................. 451 Master Address register ..................................................................... 452 Register................................................................................. 452 Register bit assignment .............................................................. 453 Slave Address register....................................................................... 453 Register..........................
ADC Configuration register..................................................................475 ADC Clock Configuration register ..........................................................477 ADC Output Registers 0-7 ...................................................................477 C h a p t e r 1 6 : T i m i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 Electrical characteristics .................................................
..... Clock timing .................................................................................. 511 System PLL reference clock timing................................................. 511 C h a p t e r 1 7 : P a c k a g i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 Package........................................................................................ 513 Processor Dimensions .................................................
Hardware Reference NS9215
Pinout (265) C H A P T E R 1 T he NS9215 offers a connection to a 10/100 Ethernet network, as well as a glueless connection to SDRAM, PC100 DIMM, flash, EEPROM, and SRAM memories, and an external bus expansion module. It includes four multi-function serial ports, one I2C channel, 12-bit Analog to Digital converter, battery backed real time clock and an AES data encryption/decryption module.
PINOUT (265) Memory bus interface Memory bus interface .................................................................................. Pin Signal B9 I/O OD Description clk_out[0] O 4 SDRAM bus clock A15 clk_out[1] O 4 SDRAM bus clock P12 addr[27] / gpio_a[3]a U I/O 4 Address bus, Endian T14 addr[26] / gpio_a[2] a. U I/O 4 Address bus, SPI boot U15 addr[25] / gpio_a[1]a. U I/O 4 Address bus R12 addr[24] / gpio_a[0] a.
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PINOUT (265) Ethernet interface MAC Pin Signal A10 U/D I/O OD Description data_mask[3] O 4 byte_enable data[31:24} B11 data_mask[2] O 4 Byte enable data[23:16] B10 data_mask[1] O 4 Byte enable data[15:08] A11 data_mask[0] O 4 Byte enable data {07:00] A9 ns_ta_strb I A6 rw_n O 4 Transfer direction B7 clk_en[3] O 4 SDRAM clock enable D7 clk_en[2] O 4 SDRAM clock enable A7 clk_en[1] O 4 SDRAM clock enable B8 clk_en[0] O 4 SDRAM clock enable B4 cs[7] O
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PINOUT (265) General purpose I/O (GPIO) Note: All GPIOs except 12 and 16 to 31 are reset to mode 3, input. GPIO 12 is reset to mode 2, reset_done. GPIO 16 to 31 are reset to mode 0, external memory data 15:0.
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PINOUT (265) General purpose I/O (GPIO) Pin Signal U/D I/O OD Description D3 gpio[16] U I/O 4 0 1 2 3 data[0] DCD UART B Ext Int Ch 0 (dup) gpio[16] B2 gpio[17] U I/O 4 0 1 2 3 data[1] CTS UART B Ext Int Ch 1 (dup) gpio[17] C2 gpio[18] U I/O 4 0 1 2 3 data[2] DSR UART B Ext Int Ch 2 (dup) gpio[18] D4 gpio[19] U I/O 4 0 1 2 3 data[3] RXD UART B EXT INT CH 3 (dup) gpio[19] B1 gpio[20] U I/O 4 0 1 2 3 data[4] RI UART B Ext DMA Done Ch 0 (dup) gpio[20] E3 gpio[21] U
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PINOUT (265) General purpose I/O (GPIO) Pin Signal U/D I/O OD Description D17 gpio[36] U I/O 2 0 1 2 3 Ethernet MII RX DV PIC_0_GEN_IO[4](I/O)(dup) Reserved gpio[36] C17 gpio[37] U I/O 2 0 1 2 3 Ethernet MII RX ER PIC_0_GEN_IO[5](I/O)(dup) Reserved gpio[37] D13 gpio[38] U I/O 2 0 1 2 3 Ethernet MII RXD[0] PIC_0_GEN_IO[6](I/O)(dup) Reserved gpio[38] B17 gpio[39] U I/O 2 0 1 2 3 Ethernet MII RXD[1] PIC_0_GEN_IO[7](I/O)(dup) Reserved gpio[39] D16 gpio[40] U I/O 2 0 1 2
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PINOUT (265) General purpose I/O (GPIO) Pin Signal U/D I/O OD Description J4 gpio[56] U I/O 2 0 1 2 3 RTS/RS485 Control UART B (dup) PIC_0_BUS_1[13](I/O) PIC_1_BUS_1[13](I/O) gpio[56] K3 gpio[57] U I/O 2 0 1 2 3 TXC/DTR UART B (dup) PIC_0_BUS_1[14](I/O) PIC_1_BUS_1[14](I/O) gpio[57] K4 gpio[58] U I/O 2 0 1 2 3 TXD UART B (dup) PIC_0_BUS_1[15](I/O) PIC_1_BUS_1[15](I/O) gpio[58] K5 gpio[59] U I/O 2 0 1 2 3 DCD UART D (dup) PIC_0_BUS_1[16](I/O) PIC_1_BUS_1[16](I/O) gpio[59]
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PINOUT (265) General purpose I/O (GPIO) Pin Signal U/D I/O OD Description T15 gpio[76] U I/O 2 0 1 2 3 PIC_0_CTL_IO[0](I/O) PIC_1_CTL_IO[0](I/O) Ext Timer Event in Ch 2 gpio[76] T16 gpio[77] U I/O 2 0 1 2 3 PIC_0_CTL_IO[1](I/O) PIC_1_CTL_IO[1](I/O) Ext Timer Event in Ch 3 gpio[77] R14 gpio[78] U I.
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PINOUT (265) General purpose I/O (GPIO) Pin Signal U/D I/O OD Description C16 gpio[96] U I/O 2 0 1 2 3 PIC_0_BUS_1[0](I/O) PIC_1_BUS_1[0](I/O) PIC_0_CAN_RXD(I)(dup) gpio[96] B16 gpio[97] U I/O 2 0 1 2 3 PIC_0_BUS_1[1](I/O) PIC_1_BUS_1[1](I/O) PIC_0_CAN_TXD(O)(dup) gpio97 D15 gpio[98] U I/O 2 0 1 2 3 PIC_0_BUS_1[2](I/O) PIC_1_BUS_1[2](I/O) PIC_1_CAN_RXD(I)(dup) gpio[98] E8 gpio[99] U I/O 2 0 1 2 3 PIC_0_BUS_1[3](I/O) PIC_1_BUS_1[3](I/O) PIC_1_CAN_TXD(O)(dup) gpio[99] D8 g
..... PINOUT (265) System clock Pin Signal U/D I/O OD Description T14 gpio_a[2] U I/O 4 0 1 2 3 addr[26] Reserved 1 cs0_we_n Ext Int Ch 2 (dup) gpio_a[2], SPI boot P12 gpio_a[3] U I/O 4 0 1 2 3 addr[27] Reserved 1 cs0_oe_n UART ref clock gpio_a[3], Endian a. There is a possible conflict when gpio12 is used as the I2C_SDA signal.
PINOUT (265) System clock System clock drawing 44 Hardware Reference NS9215
..... PINOUT (265) System mode RTC clock and battery backup drawing Note: If RTC battery backup is not used, the following connection changes can be made. N3, M4 bat_vdd_reg tie to 1.8V 32.788kHz crystal load capacitors tie to N3, M4 (1.8V) N4 bat_vdd tie to 3.3V R1 aux_comp tie to ground System mode ..................................................................................
PINOUT (265) System mode sys_mode_2 sys_mode_1 sys_mode_0 Description 0 0 0 manufacturing test 0 0 1 manufacturing test 0 1 0 manufacturing test 0 1 1 normal operation, boundary scan enabled, POR disabled 1 0 0 normal operation, boundary scan enabled, POR enabled 1 0 1 board test mode, all outputs tristated 1 1 0 normal operation, ARM debug enabled, POR disabled 1 1 1 normal operation, ARM debug enabled, POR enabled 46 Hardware Reference NS9215
..... PINOUT (265) System reset System reset .................................................................................. Pin Signal U/D I/O E12 reset_n U I A5 reset_out_n O 2 System reset output A13 reset_done O 2 Reset done D9 sreset_n U OD Description System reset I Soft system reset RESET_n pin SRESET_n pin PLL Config Reg.
PINOUT (265) JTAG Test JTAG Test .................................................................................. 48 Pin Signal U/D I/O N14 tdi U I N15 tdo T17 tms U I Test mode select R16 trst_n U I Test mode reset. For normal operation, this pin is tied to ground or pulled down.
..... PINOUT (265) ADC ADC .................................................................................. Pin Signal U/D I/O OD Description P4 agnd_ref_adc Analog reference ground P5 VREF_adc Analog reference voltage (3.3max T2 vss_adc ADC_VSS N6 vdd_adc ADC VDD (3.
PINOUT (265) POR and battery-backed logic POR and battery-backed logic .................................................................................. Pin Signal U/D M3 por_gnd_reg POR reference ground N2 por_vss POR VSS P1 por_vdd POR VDD (3.3V) L3 por_reference POR reference trip voltage (2.74V min / 2.97V max) T1 por_early_reference POR early power loss voltage (1.19V min / 1.28V max) N4 bat_vdd Battery VDD (3.0V) R1 aux_comp Auxiliary analog comparator input (trip point 2.
..... PINOUT (265) Power and ground If the RTC feature is not used, the inputs must be terminated as shown below. N4 Bat_vdd tie to 3.3V R1 aux_comp tie to ground N3, M4 bat_vdd_reg tie to ground P2 x1_rtc_osc tie to ground R2 x2_rtc_osc leave open If the RTC feature is used, see RTC clock and battery backup drawing on page 45. Power and ground ..................................................................................
PINOUT (265) Power and ground 52 Hardware Reference NS9215
I/O Control Module C H A P T E R 2 T he NS9215 ASIC contains 108 pins that are designated as general purpose I/O (GPIO). The first 16 GPIO can be configured to serve one of five functions. The remaining GPIO can be configured to serve one of four functions. All signals set to a disabled peripheral are held in the inactive state. The I/O control module contains the control register and multiplexing logic required to accomplish this task.
I/O CONTROL MODULE Control and Status registers 54 Address Description Access Reset value A090_200C GPIO Configuration Register #3 R/W 0x18181810 A090_2010 GPIO Configuration Register #4 R/W 0x00000000 A090_2014 GPIO Configuration Register #5 R/W 0x00000000 A090_2018 GPIO Configuration Register #6 R/W 0x00000000 A090_201C GPIO Configuration Register #7 R/W 0x00000000 A090_2020 GPIO Configuration Register #8 R/W 0x18181818 A090_2024 GPIO Configuration Register #9 R/W 0x18181
..... I/O CONTROL MODULE GPIO Configuration registers Address Description Access Reset value A090_208C Memory Bus Configuration register R/W 007D6344 1 The reset values for all the status bits are undefined because they depend on the state of the GPIO pins to NS9215. GPIO Configuration registers .................................................................................. GPIO Configuration registers #0 through #26 contain the configuration information for each of the 108 GPIO pins.
I/O CONTROL MODULE GPIO Configuration registers Address: A090_2000 GPIO Configuration Register #0 31 30 29 28 27 26 25 24 23 22 21 20 GPIO3 15 14 13 12 18 17 16 2 1 0 18 17 16 2 1 0 GPIO2 11 10 9 8 7 6 5 4 GPIO1 3 GPIO0 Bit(s) Access Mnemonic Reset Description D31:24 R/W GPIO3 0x18 GPIO[3] configuration D23:16 R/W GPIO2 0x18 GPIO[2] configuration D15:08 R/W GPIO1 0x18 GPIO[1] configuration D07:00 R/W GPIO0 0x18 GPIO[0] configuration Addres
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I/O CONTROL MODULE GPIO Configuration registers Address: A090_2010 GPIO Configuration Register #4 31 30 29 28 27 26 25 24 23 22 21 20 GPIO19 15 14 13 12 18 17 16 2 1 0 18 17 16 2 1 0 GPIO18 11 10 9 8 7 6 5 4 GPIO17 3 GPIO16 Bit(s) Access Mnemonic Reset Description D31:24 R/W GPIO19 0x00 GPIO[19] configuration D23:16 R/W GPIO18 0x00 GPIO[18] configuration D15:08 R/W GPIO17 0x00 GPIO[17] configuration D07:00 R/W GPIO16 0x00 GPIO[16] configur
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I/O CONTROL MODULE GPIO Configuration registers Address: A090_2020 GPIO Configuration Register #8 31 30 29 28 27 26 25 24 23 22 21 20 GPIO35 15 14 13 12 11 18 17 16 2 1 0 18 17 16 2 1 0 GPIO34 10 9 8 7 6 5 4 GPIO33 3 GPIO32 Bit(s) Access Mnemonic Reset Description D31:24 R/W GPIO35 0x18 GPIO[35] configuration D23:16 R/W GPIO34 0x18 GPIO[34] configuration D15:08 R/W GPIO33 0x18 GPIO[33] configuration D07:00 R/W GPIO32 0x18 GPIO[32] configura
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I/O CONTROL MODULE GPIO Configuration registers Address: A090_2030 GPIO Configuration Register #12 31 30 29 28 27 26 25 24 23 22 21 20 GPIO51 15 14 13 12 17 16 11 10 9 8 7 6 5 4 3 2 1 0 18 17 16 2 1 0 GPIO48 Bit(s) Access Mnemonic Reset Description D31:24 R/W GPIO51 0x18 GPIO[51] configuration D23:16 R/W GPIO50 0x18 GPIO[50] configuration D15:08 R/W GPIO49 0x18 GPIO[49] configuration D07:00 R/W GPIO48 0x18 GPIO[48] configuration Address: A090
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I/O CONTROL MODULE GPIO Configuration registers GPIO Configuration Register #16 Address: A090_2040 31 30 29 28 27 26 25 24 23 22 21 GPIO67 15 14 13 12 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 18 17 16 2 1 0 GPIO64 Bit(s) Access Mnemonic Reset Description D31:24 R/W GPIO67 0x18 GPIO[67] configuration D23:16 R/W GPIO66 0x18 GPIO[66] configuration D15:08 R/W GPIO65 0x18 GPIO[65] configuration D07:00 R/W GPIO64 0x18 GPIO[64] configuration Address: A09
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I/O CONTROL MODULE GPIO Configuration registers Address: A090_2050 GPIO Configuration Register #20 31 30 29 28 27 26 25 24 23 22 21 GPIO83 15 14 13 12 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 18 17 16 2 1 0 GPIO80 Bit(s) Access Mnemonic Reset Description D31:24 R/W GPIO83 0x18 GPIO[83] configuration D23:16 R/W GPIO82 0x18 GPIO[82] configuration D15:08 R/W GPIO81 0x18 GPIO[81] configuration D07:00 R/W GPIO80 0x18 GPIO[80] configuration Address: A090
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I/O CONTROL MODULE GPIO Configuration registers GPIO Configuration Register #24 Address: A090_2060 31 30 29 28 27 26 25 24 23 22 21 GPIO99 15 14 13 12 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 18 17 16 2 1 0 GPIO96 Bit(s) Access Mnemonic Reset Description D31:24 R/W GPIO99 0x18 GPIO[99] configuration D23:16 R/W GPIO98 0x18 GPIO[98] configuration D15:08 R/W GPIO97 0x18 GPIO[97] configuration D07:00 R/W GPIO96 0x18 GPIO[96] configuration Address: A09
..... I/O CONTROL MODULE GPIO Configuration registers GPIO Configuration Register #26 Address: A090_2068 31 30 29 28 27 26 25 24 23 22 21 GPIO_A3 15 14 13 12 11 19 18 17 16 2 1 0 GPIO_A2 10 9 8 7 GPIO_A1 www.digiembedded.
I/O CONTROL MODULE GPIO Control registers GPIO Control registers .................................................................................. GPIO Control Registers #0 through #3 contain the control information for each of the 108 GPIO pins. When a GPIO pin is configured as a GPIO output, the corresponding bit in GPIO Control Registers #0 through #3 is driven out the GPIO pin. In all configurations, the CPU has read/write access to these registers.
..... I/O CONTROL MODULE GPIO Control registers GPIO Control Register #1 www.digiembedded.
I/O CONTROL MODULE GPIO Control registers GPIO Control Register #2 72 Bit(s) Access Mnemonic Reset Description D22 R/W GPIO54 0 GPIO[54] control bit D23 R/W GPIO55 0 GPIO[55] control bit D24 R/W GPIO56 0 GPIO[56] control bit D25 R/W GPIO57 0 GPIO[57] control bit D26 R/W GPIO58 0 GPIO[58] control bit D27 R/W GPIO59 0 GPIO[59] control bit D28 R/W GPIO60 0 GPIO[60] control bit D29 R/W GPIO61 0 GPIO[61] control bit D30 R/W GPIO62 0 GPIO[62] control bit D31
..... I/O CONTROL MODULE GPIO Control registers GPIO Control Register #3 www.digiembedded.
I/O CONTROL MODULE GPIO Status registers GPIO Status registers .................................................................................. GPIO Status Registers #0 through #3 contain the status information for each of the 108 GPIO pins. In all configurations, the value on the GPIO input pin is brought to the status register and the CPU has read-only access to the register.
..... I/O CONTROL MODULE GPIO Status registers GPIO Status Register #2 www.digiembedded.
I/O CONTROL MODULE Memory Bus Configuration register GPIO Status Register #3 Bit(s) Access Mnemonic Reset Description D23 R GPIO87 Undefined GPIO[87] status bit D24 R GPIO88 Undefined GPIO[88] status bit D25 R GPIO89 Undefined GPIO[89] status bit D26 R GPIO90 Undefined GPIO[90] status bit D27 R GPIO91 Undefined GPIO[91] status bit D28 R GPIO92 Undefined GPIO[92] status bit D29 R GPIO93 Undefined GPIO[93] status bit D30 R GPIO94 Undefined GPIO[94] status bit D3
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I/O CONTROL MODULE Memory Bus Configuration register Bit(s) Access Mnemonic Reset Description D14:12 R/W CS4 0x6 Controls which system memory chip select is routed to CS4 000 001 010 011 100 101 110 111 D17:15 R/W CS5 0x2 dy_cs_0 dy_cs_1 dy_cs_2 dy_cs_3 st_cs_0 st_cs_1 st_cs_2 (default) st_cs_3 Controls which system memory chip select is routed to CS5 000 001 010 011 100 101 110 111 D20:18 R/W CS6 0x7 dy_cs_0 dy_cs_1 dy_cs_2 (default) dy_cs_3 st_cs_0 st_cs_1 st_cs_2 st_cs_3 Controls w
..... I/O CONTROL MODULE Memory Bus Configuration register Bit(s) Access Mnemonic Reset Description D25 R/W APUDIS 0x0 Address bus pullup control (Applicable only to address associated with hardware strapping) 0 1 Enable pullup resistors Disable pullup resistors Note: D31:26 www.digiembedded.
I/O CONTROL MODULE Memory Bus Configuration register 80 Hardware Reference NS9215
Working with the CPU C H A P T E R 3 T his processor core is based on the ARM926EJ-S processor. The ARM926EJ-S processor belongs to the ARM9 family of general-purpose microprocessors. The ARM926EJ-S processor is targeted at multi-tasking applications in which full memory management, high performance, low die size, and low power are important.
WO R K I N G W I T H T H E C P U Instruction sets This drawing shows the main blocks in the ARM926EJ-S processor. Arm926EJ-S process block diagram DEXT Write buffer DROUTE DCACHE Cache PA TAGRAM WDATA RDATA DA writeback write buffer MMU DMVA ARM926EJ-S INSTR FCSE IMVA Data AHB interface AHB Bus interface unit TLB IA Instruction AHB interface AHB ICACHE IROUTE IEXT Instruction sets ..................................................................................
..... WO R K I N G W I T H T H E C P U System control processor (CP15) registers Java instruction set In Java state, the processor core executes a majority of Java bytecodes naturally. Bytecodes are decoded in two states, compared to a single decode stage when in ARM/Thumb mode. See “Jazelle(Java)” on page 104 for more information about Java. System control processor (CP15) registers ..................................................................................
WO R K I N G W I T H T H E C P U System control processor (CP15) registers 31 28 27 26 25 24 23 Cond 1 1 1 0 21 20 19 Opcode _1 L 16 15 CRn 12 11 10 9 8 1 1 1 Rd 1 7 5 Opcode _2 4 3 1 0 CRm Figure 1: CP15 MRC and MCR bit pattern The mnemonics for these instructions are: MCR{cond} p15,opcode_1,Rd,CRn,CRm,opcode_2 MRC{cond} p15,opcode_1,Rd,CRn,CRm,opcode_2 If you try to read from a write-only register or write to a read-only register, you will have UNPREDICTABLE results.
..... WO R K I N G W I T H T H E C P U System control processor (CP15) registers Note: Register summary In all cases, reading from or writing any data values to any CP15 registers, including those fields specified as UNPREDICTABLE, SHOULD BE ONE, or SHOULD BE ZERO, does not cause any physical damage to the chip. CP15 uses 16 registers. Register locations 0, 5, and 13 each provide access to more than one register.
WO R K I N G W I T H T H E C P U R0: ID code and cache type status registers The B bit is set to 0 at reset if the BIGENDINIT signal is low, and set to 1 if the BIGENDINIT signal is high. R0: ID code and cache type status registers .................................................................................. Register R0 access the ID register, and cache type register.
..... WO R K I N G W I T H T H E C P U R0: ID code and cache type status registers You can access the cache type register by reading CP15 register R0 with the opcode_2 field set to 1. Note this example: MRC p15, 0, Rd, c0, c0, 1; returns cache details Cache type register and field description 31 0 28 0 0 25 24 23 Ctype 12 Dsize S Isize Field Description Ctype Determines the cache type, and specifies whether the cache supports lockdown and how it is cleaned.
WO R K I N G W I T H T H E C P U R1: Control register Field Description Size Determines the cache size in conjunction with the M bit. The M bit is 0 for DCache and ICache. The size field is bits [21:18] for the DCache and bits [9:6] for the ICache. The minimum size of each cache is 4 KB; the maximum size is 128 KB. Cache size encoding with M=0: Size field Cache size 0b0011 4 KB 0b0100 8 KB Note: Assoc The processor always reports 4KB for DCache and 8KB for ICache.
..... WO R K I N G W I T H T H E C P U R1: Control register Control register 31 19 18 17 16 15 14 13 12 11 10 9 S B O SBZ S B Z S B O L 4 R R V I SBZ R 8 7 S B 6 SBO 3 2 1 0 C A M Bit functionality Bits Name Function [31:19] N/A Reserved: When read, returns an UNPREDICTABLE value. When written, SHOULD BE ZERO, or a value read from bits [31:19] on the same processor. Use a read-modify-write sequence when modifying this register to provide the greatest future compatibility.
WO R K I N G W I T H T H E C P U R1: Control register Bits Name Function [6:3] N/A Reserved. SHOULD BE ONE.
..... WO R K I N G W I T H T H E C P U R2: Translation Table Base register R2: Translation Table Base register .................................................................................. Register R2 is the Translation Table Base register (TTBR), for the base address of the first-level translation table. Reading from R2 returns the pointer to the currently active first-level translation table in bits [31:14] and an UNPREDICTABLE value in bits [13:0].
WO R K I N G W I T H T H E C P U R4 register R4 register .................................................................................. Accessing (reading or writing) this register causes UNPREDICTABLE behavior. R5: Fault Status registers .................................................................................. Register R5 accesses the Fault Status registers (FSRs). The Fault Status registers contain the source of the last instruction or data fault.
..... WO R K I N G W I T H T H E C P U R6: Fault Address register Status and domain fields This table shows the encodings used for the status field in the Fault Status register, and indicates whether the domain field contains valid information. See “MMU faults and CPU aborts” on page 119 for information about MMU aborts in Fault Address and Fault Status registers.
WO R K I N G W I T H T H E C P U R7:Cache Operations register R7:Cache Operations register .................................................................................. Register R7 controls the caches and write buffer. The function of each cache operation is selected by the opcode_2 and CRm fields in the MCR instruction that writes to CP15 R7. Writing other opcode_2 or CRm values is UNPREDICTABLE.
..... WO R K I N G W I T H T H E C P U R7:Cache Operations register Function Description Drain write buffer Acts as an explicit memory barrier. This instruction drains the contents of the write buffers of all memory stores occurring in program order before the instruction is completed. No instructions occurring in program order after this instruction are executed until the instruction completes.
WO R K I N G W I T H T H E C P U R7:Cache Operations register Modified virtual address format (MVA) Function/operation Data format Instruction Drain write buffer SBZ MCR p15, 0, Rd, c7, c10, 4 Wait for interrupt SBZ MCR p15, 0, Rd, c7, c0, 4 This is the modified virtual address format for Rd for the CP15 R7 MCR operations. 31 S+5 S+4 5 4 Set(=index) Tag 2 1 Word 0 SBZ The tag, set, and word fields define the MVA. For all cache operations, the word field SHOULD BE ZERO.
..... WO R K I N G W I T H T H E C P U R8:TLB Operations register Note: The test and clean DCache instruction MRC p15, 0, r15, c7, c10, 3 is a special encoding that uses r15 as a destination operand. The PC is not changed by using this instruction, however. This MRC instruction also sets the condition code flags. If the cache contains any dirty lines, bit 30 is set to 0. If the cache contains no dirty lines, bit 30 is set to 1.
WO R K I N G W I T H T H E C P U R9: Cache Lockdown register Operation Data Instruction Invalidate set-associative TLB SBZ MCR p15, 0, Rd, c8, c6, 0 Invalidate single entry MVA MCR p15, 0, Rd, c8, c6, 1 The invalidate TLB operations invalidate all the unpreserved entries in the TLB. The invalidate TLB single entry operations invalidate any TLB entry corresponding to the modified virtual address given in Rd, regardless of its preserved state.
..... WO R K I N G W I T H T H E C P U R9: Cache Lockdown register Instruction or data lockdown register Access instructions Modifying the Cache Lockdown register The first four bits of this register determine the L bit for the associated cache way. The opcode_2 field of the MRC or MCR instruction determines whether the instruction or data lockdown register is accessed: opcode_2=0 Selects the DCache Lockdown register, or the Unified Cache Lockdown register if a unified cache is implemented.
WO R K I N G W I T H T H E C P U R9: Cache Lockdown register Lockdown cache: Specific loading of addresses into a cache-way Bits 4-way associative Notes [3] L bit for way 3 Bits [3:0] are the L bits for each cache way: [2] L bit for way 2 0 [1] L bit for way 1 1 [0] L bit for way 0 Allocation to the cache way is determined by the standard replacement algorithm (reset state) No allocation is performed to this way Use this procedure to lockdown cache.
..... WO R K I N G W I T H T H E C P U R10:TLB Lockdown register Write ==0 to Cache Lockdown register (R9), setting L==1 for bit i and restoring all other bits to the values they had before the lockdown routine was started. 8 Cache unlock procedure To unlock the locked down portion of the cache, write to Cache Lockdown register (R9) setting L==0 for the appropriate bit.
WO R K I N G W I T H T H E C P U R11 and R12 registers Programming instructions Use these instructions to program the TLB Lockdown register: Function Instruction Read data TLB lockdown victim MRC p15, 0, Rd, c10, c0, 0 Write data TLB lockdown victim MCR p15, 0, Rd, c10, c0, 0 The victim automatically increments after any table walk that results in an entry being written into the lockdown part of the TLB.
..... WO R K I N G W I T H T H E C P U R13:Process ID register opcode_2=1 Selects the context ID register. Use the Process ID register to determine the process that is currently running. The process identifier is set to 0 at reset. FCSE PID register Addresses issued by the ARM926EJ-S core, in the range 0 to 32 MB, are translated according to the value contained in the FCSE PID register. Address A becomes A + (FCSE PID x 32 MB); it is this modified address that the MMU and caches see.
WO R K I N G W I T H T H E C P U R14 register A1, A2, and A3 are the three instructions following the fast context switch. Context ID register The Context ID register provides a mechanism that allows real-time trace tools to identify the currently executing process in multi-tasking environments.
..... WO R K I N G W I T H T H E C P U DSP Software emulation within the ARM-optimized JVM, which addresses the remaining 20% of the Java byte codes. DSP .................................................................................. The ARM926EJ-S processor core provides enhanced DSP capability. Multiply instructions are processed using a single cycle 32x16 implementation.
WO R K I N G W I T H T H E C P U MemoryManagement Unit (MMU) Invalidate entire TLB using R8: TLB Operations register (see “R8:TLB Operations register” on page 97). Invalidate TLB entry selected by MVA, using R8: TLB Operations register (see “R8:TLB Operations register” on page 97). Lockdown of TLB entries using R10: TLB Lockdown register (see “R10:TLB Lockdown register” on page 101).
..... WO R K I N G W I T H T H E C P U MemoryManagement Unit (MMU) MMU program accessible registers This table shows the CP15 registers that are used in conjunction with page table descriptors stored in memory to determine MMU operation. Register Bits Description R1: Control register M, A, S, R Contains bits to enable the MMU (M bit), enable data address alignment checks (A bit), and to control the access protection scheme (S bit and R bit).
WO R K I N G W I T H T H E C P U MemoryManagement Unit (MMU) The MMU table-walking hardware adds entries to the TLB. The translation information that comprises both the address translation data and the access permission data resides in a translation table located in physical memory. The MMU provides the logic for automatically traversing this translation table and loading entries into the TLB. The number of stages in the hardware table walking and permission checking process is one or two.
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WO R K I N G W I T H T H E C P U MemoryManagement Unit (MMU) First-level fetch concatenation and address Modified virtual address 31 20 19 0 Table index Translation table base 31 14 13 0 Translation base 31 21 0 14 13 Translation base Table index 31 00 0 First-level descriptor This address selects a 4-byte translation table entry. This is a first-level descriptor for either a section or a page.
..... WO R K I N G W I T H T H E C P U MemoryManagement Unit (MMU) First-level descriptor bit assignments: Priority encoding of fault status First-level descriptor bit assignments: Interpreting first level descriptor bits [1:0] Section descriptor Section descriptor format Bits Section Coarse Fine Description [31:20] [31:10] [31:12] Forms the corresponding bits of the physical address. [19:12] ---- --- SHOULD BE ZERO [11:10] --- --- Access permission bits.
WO R K I N G W I T H T H E C P U MemoryManagement Unit (MMU) Section descriptor bit description Coarse page table descriptor Bits Description [31:20] Forms the corresponding bits of the physical address for a section. [19:12] Always written as 0. [11:10] Specify the access permissions for this section. [09] Always written as 0. [8:5] Specifies one of the 16 possible domains (held in the Domain and Access Control register) that contain the primary access controls.
..... WO R K I N G W I T H T H E C P U MemoryManagement Unit (MMU) page tables have 1024 entries, splitting the 1 MB that the table describes into 1 KB blocks. The next two sections show the format of a fine page table descriptor and define the fine page table descriptor bit assignments. Note: Fine page table descriptor format If a fine page table descriptor is returned from the first-level fetch, a second-level fetch is initiated.
WO R K I N G W I T H T H E C P U MemoryManagement Unit (MMU) 31 20 19 0 Table index Section index Translation table base 31 14 13 0 14 13 2 10 Translation base 31 Translation base Table index 0 0 Section first-level descriptor 31 20 19 8 SBZ Section base address AP 54 3 2 1 0 0 Domain 1 C B 0 1 Physical address 31 20 19 0 Section index Section base address Second-level descriptor The base address of the page table to be used is determined by the descriptor returned (if any) from
..... WO R K I N G W I T H T H E C P U MemoryManagement Unit (MMU) A tiny page descriptor provides the base address of a 1 KB block of memory. Coarse page tables provide base addresses for either small or large pages. Large page descriptors must be repeated in 16 consecutive entries. Small page descriptors must be repeated in each consecutive entry. Fine page tables provide base addresses for large, small, or tiny pages. Large page descriptors must be repeated in 64 consecutive entries.
WO R K I N G W I T H T H E C P U MemoryManagement Unit (MMU) Translation sequence for large page references Modified virtual address 31 1615 20 19 Table index table index 12 11 0 Page index Translation table base 31 14 13 0 14 13 2 1 0 Translation base 31 Translation base Table index 0 0 First-level descriptor 31 10 9 8 54 3 2 1 0 Domain 1 Coarse page table base address 31 10 9 2 1 0 L2 table index Coarse page table base address 0 1 0 0 Second-level descriptor 31 1615 121110 9
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WO R K I N G W I T H T H E C P U MemoryManagement Unit (MMU) Translation sequence for tiny page references Modified virtual address 31 10 9 20 19 Level two table index Table index 0 Page index Translation table base 31 14 13 0 14 13 2 1 0 Translation base 31 Translation base Table index 0 0 First-level descriptor 31 12 11 8 Domain 1 Fine page table base address 31 54 3 2 1 0 12 11 1 1 2 1 0 L2 table index Fine page table base address 0 0 Second-level descriptor 31 10 9 Page bas
..... WO R K I N G W I T H T H E C P U MMU faults and CPU aborts When you use subpage permissions and the page entry has to be invalidated, you must invalidate all four subpages separately. MMU faults and CPU aborts ..................................................................................
WO R K I N G W I T H T H E C P U MMU faults and CPU aborts register. If an access violation simultaneously generates more than one source of abort, the aborts are encoded in the priority shown in the priority encoding table. The Fault Address register is not updated by faults caused by instruction prefetches.
..... WO R K I N G W I T H T H E C P U Domain access control Domain Fault Address register Domain MVA of first aborted address in transfer Permission MVA of first aborted address in transfer External about for noncached reads, or nonbuffered writes MVA of last address before 1KB boundary, if any word of the transfer before 1 KB boundary is externally aborted. MVA of last address in transfer if the first externally aborted word is after the 1 KB boundary.
WO R K I N G W I T H T H E C P U Fault checking sequence AP S R Privileged permissions User permissions 00 0 0 No access No access 00 1 0 Read only Read only 00 0 1 Read only Read only 00 1 1 UNPREDICTABLE UNPREDICTABLE 01 x x Read/write No access 10 x x Read/write Read only 11 x x Read/write Read/write Fault checking sequence ..................................................................................
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WO R K I N G W I T H T H E C P U Fault checking sequence Note: Translation faults If an access generates an alignment fault, the access sequence aborts without reference to other permission checks. There are two types of translation fault: section and page. A section translation fault is generated if the level one descriptor is marked as invalid. This happens if bits [1:0] of the descriptor are both 0. A page translation fault is generated if the level one descriptor is marked as invalid.
..... WO R K I N G W I T H T H E C P U External aborts interpreted in the same way as for a section (see “Interpreting access permission bits” on page 121). The only difference is that the fault generated is a page permission fault. Tiny page: If the level one descriptor defines a page-mapped access and the level two descriptor is for a tiny page, the AP bits of the level one descriptor define whether the access is allowed in the same way as for a section. The fault generated is a page permission fault.
WO R K I N G W I T H T H E C P U TLB structure Care must be taken if the translated address differs from the untranslated address, because several instructions following the enabling of the MMU might have been prefetched with MMU off (VA=MVA=PA). If this happens, enabling the MMU can be considered as a branch with delayed execution. A similar situation occurs when the MMU is disabled.
..... WO R K I N G W I T H T H E C P U Caches and write buffer about the structure, replacement algorithm, or persistence of entries in the set-associative part — specifically: Any entry written into the set-associative part of the TLB can be removed at any time. The set-associative part of the TLB must be considered as a temporary cache of translation/page table information.
WO R K I N G W I T H T H E C P U Caches and write buffer The caches use pseudo-random or round-robin replacement, selected by the RR bit in R1: Control register. Cache lockdown registers enable control over which cache ways are used for allocation on a linefill, providing a mechanism for both lockdown and controlling cache pollution.
..... WO R K I N G W I T H T H E C P U Caches and write buffer ICache I and M bit settings ICache page table C bit settings R1 register C and M bits for DCache DCache page table C and B settings www.digiembedded.com This table gives the I and M bit settings for the ICache, and the associated behavior. R1 I bit R1 M bit ARM926EJ-S behavior 0 ----- ICache disabled. All instruction fetches are fetched from external memory (AHB). 1 0 ICache enabled, MMU disabled.
WO R K I N G W I T H T H E C P U Cache MVA and Set/Way formats Page table C bit Page table B bit Description ARM926EJ-S behavior 0 0 Noncachable, nonbufferable DCache disabled. Read from external memory. Write as a nonbuffered store(s) to external memory. DCache is not updated. 0 1 Noncachable, bufferable DCache disabled. Read from external memory. Write as a buffered store(s) to external memory. DCache is not updated.
..... WO R K I N G W I T H T H E C P U Cache MVA and Set/Way formats Generic, virtually indexed, virtually addressed cache Tag Index 0 1 2 3 4 5 6 7 Byte 0 TAG n 0 1 Hit www.digiembedded.
WO R K I N G W I T H T H E C P U Cache MVA and Set/Way formats ARM926EJ-S cache format S+5 S+4 31 5 4 Index Tag 0 1 2 3 4 5 6 7 Word 0 Byte TAG n 0 ARM926EJ-S cache associativity 2 1 1 2 3 The following points apply to the ARM926EJ-S cache associativity: The group of tags of the same index defines a set. The number of tags in a set is the associativity. The ARM926EJ-S caches are 4-way associative. The range of tags addressed by the index defines a way.
..... WO R K I N G W I T H T H E C P U Noncachable instruction fetches In this figure: A = log2 associativity For example, with a 4-way cache A = 2: S = log2 NSETS Noncachable instruction fetches .................................................................................. The ARM926EJ-S processor performs speculative noncachable instruction fetches to increase performance. Speculative instruction fetching is enabled at reset.
WO R K I N G W I T H T H E C P U Noncachable instruction fetches AHB behavior If instruction prefetching is disabled, all instruction fetches appear on the AHB interface as single, nonsequential fetches. If prefetching is enabled, instruction fetches appear either as bursts of four instructions or as single, nonsequential fetches. No speculative instruction fetching is done across a 1 KB boundary. All instruction fetches, including those made in Thumb state, are word transfers (32 bits).
..... WO R K I N G W I T H T H E C P U Noncachable instruction fetches recommended that either a nonbuffered store (STR) or a noncached load (LDR) be used to trigger external synchronization. Sample IMB sequences 4 Invalidate the cache. The ICache must be invalidated to remove any stale copies of instructions that are no longer valid. If the ICache is not being used, or the modified regions are not in cachable areas of memory, this step might not be required. 5 Flush the prefetch buffer.
WO R K I N G W I T H T H E C P U Noncachable instruction fetches 136 Hardware Reference NS9215
System Control Module C H A P T E R 4 T he System Control Module configures and oversees system operations for the processor, and defines both the AMBA High-speed Bus (AHB) arbiter system and system memory address space.
SYSTEM CONTROL MODULE System bus arbiter System bus arbiter .................................................................................. The bus arbitration mechanism ensures that only one bus master has access to the system bus at any time. If you are using a system in which bus bandwidth allocation is critical, you must be sure that your worst-case bus bandwidth allocation goals can be met. See “Arbiter configuration example” on page 140 for information about configuring the AHB arbiter.
..... SYSTEM CONTROL MODULE System bus arbiter 2 The arbiter stops evaluating the BRR until a bus grant is issued for the previous evaluation cycle. 3 The arbiter grants the bus to requesting channels, in a round-robin manner, at the rising clock edge of the last address issued for the current transaction (note that each transaction may have multiple transfers), when a SPLIT response is sampled by the arbiter, or when the bus is idling.
SYSTEM CONTROL MODULE System bus arbiter If the bus is granted to a default master and continues to be in the IDLE state longer than a specified period of time, an AHB bus arbiter timeout is generated. An AHB bus arbiter timeout can be configured to interrupt the CPU or to reset the chip. SPLIT transfers A SPLIT transfer occurs when a slave is not ready to perform the transfer.
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SYSTEM CONTROL MODULE Programmable timers Address range Size System functions 0x7000 0000 – 0x7FFF FFFF 256 MB System memory chip select 3 Static memory (default) 0x8000 0000 – 0x8FFF FFFF 256 MB Reserved 0x9000 0000 – 0x9FFF FFFF 256 MB IO hub 0xA000 0000 – 0xA05F FFFF 6 MB Reserved 0xA060 0000 – 0xA06F FFFF 1 MB Ethernet Communication Module 0xA070 0000 – 0xA07F FFFF 1 MB Memory controller 0xA080 0000 – 0xA08F FFFF 1 MB External DMA module 0xA090 0000 – 0xA09F FFFF 1 MB System
..... SYSTEM CONTROL MODULE General purpose timers/counters General purpose timers/counters .................................................................................. Ten 32-bit general purpose timers/counters (GPTC) provide programmable time intervals to the CPU when used as one or multiple timers. There are two I/O pins associated with each timer. When used as a gated timer, one I/O pin serves as an input qualifier (high/low programmable).
SYSTEM CONTROL MODULE Basic PWM function Interrupt enable Concatenate to up-stream timer/counter; that is, use up-stream timer/counter’s overflow/underflow output as clock input Reload enable Basic PWM function Enhanced PWM functionality (timers 6–9) Quadrature decoder function (timer 5) 32-bit or 16-bit operation These options are available in 16-bit mode: 16-bit mode options Capture mode. Capture the counter value on the rising or falling edge of an external event and interrupt the CPU. Compare mode.
..... SYSTEM CONTROL MODULE Enhanced PWM function Enhanced PWM function .................................................................................. Timer counters 6–9 have additional features to add enhanced PWM functionality: High register — Compared to the timer/counter to toggle PWM output high Low register — Compared to the timer/counter to toggle PWM output back low Three 15-bit Step registers associated with four enhanced timer/counters.
SYSTEM CONTROL MODULE How the quadrature decoder/counter works A quadrature decoder/counter module performs these tasks at real time speed and interrupts the CPU at the predetermined conditions. How the quadrature decoder/counter works .................................................................................. Provides input signals A quadrature encoder provides a pair of signals (in-phase and quad-phase) with opposite polarities and a 90-degree phase shift.
..... SYSTEM CONTROL MODULE How the quadrature decoder/counter works Monitors how far the encoder has moved The counter keeps a running count of how far the encoder has moved. The decoder increments a 32-bit counter when a state change is found in the positive direction. The decoder decrements a 32-bit counter when a state change is found in the other direction. When the programmed number reaches the terminal count, the counter is reset and an interrupt is generated to the CPU.
SYSTEM CONTROL MODULE Interrupt controller Interrupt controller .................................................................................. The interrupt system is a simple two-tier priority scheme. Two lines access the CPU core and can interrupt the processor: IRQ (normal interrupt) and FIQ (fast interrupt). FIQ has a higher priority than IRQ. FIQ interrupts Most sources of interrupts on the processor are from the IRQ line. There is only one FIQ source for timing-critical applications.
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SYSTEM CONTROL MODULE Interrupt controller The interrupt sources are assigned as shown: 150 Interrupt ID Interrupt source 0 Watchdog Timer 1 AHB Bus Error 2 Ext DMA 3 CPU Wake Interrupt 4 Ethernet Module Receive Interrupt 5 Ethernet Module Transmit Interrupt 6 Ethernet Phy Interrupt 7 UART A Interrupt 8 UART B Interrupt 9 UART C Interrupt 10 UART D Interrupt 11 SPI Interrupt 12 Reserved 13 Reserved 14 ADC Interrupt 15 Early Power Loss Interrupt 16 I2C Interrupt 17 RT
..... SYSTEM CONTROL MODULE Vectored interrupt controller (VIC) flow Vectored interrupt controller (VIC) flow .................................................................................. This is how the VIC flow works: 1 An interrupt occurs. 2 The CPU branches to either the IRQ or FIQ interrupt vector. 3 If the CPU goes to the IRQ vector, the CPU reads the service routine address from the VIC’s ISADDR register.
SYSTEM CONTROL MODULE Bootstrap initialization PLL configuration and control system block diagram x1_sys_osc 29.4912 MHz PLL Ref Clk OSC x2_sys_osc Clk Out BP NR[4:0] OD[1:0] set by strapping or software set by software only NF[8:0] div by 2,4,8,16,32,64, 128 (programmable) CPU clock (149.9136 MHz max) mux select default is AHB clock (CCSel = 0) div by 4,8,16,32,64,128 or 256 (programmable) main clocks to modules AHB clocks (74.
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SYSTEM CONTROL MODULE System configuration registers System configuration registers .................................................................................. All configuration registers must be accessed as 32-bit words and as single accesses only. Bursting is not allowed.
..... SYSTEM CONTROL MODULE System configuration registers www.digiembedded.
SYSTEM CONTROL MODULE System configuration registers 156 Offset [31:24] [15:8] [7:0] A090 00F8 Interrupt Vector Address Register Level 13 A090 00FC Interrupt Vector Address Register Level 14 A090 0100 Interrupt Vector Address Register Level 15 A090 0104 Interrupt Vector Address Register Level 16 A090 0108 Interrupt Vector Address Register Level 17 A090 010C Interrupt Vector Address Register Level 18 A090 0110 Interrupt Vector Address Register Level 19 A090 0114 Interrupt Vector Address
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SYSTEM CONTROL MODULE General Arbiter Control register Offset [31:24] [23:16] [15:8] A090 0214 External Interrupt 0 Control register A090 0218 External Interrupt 1 Control register A090 021C External Interrupt 2 Control register A090 0220 External Interrupt 3 Control register A090 0224 RTC Module Control A090 0228 Power Management A090 022C AHB Bus Activity Status [7:0] General Arbiter Control register ..................................................................................
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SYSTEM CONTROL MODULE AHB Error Detect Status 2 The AHB Error Detect Status 1 register records the haddr[31:0] value present when any AHB error is found. Note that this value is not reset on powerup but is reset when the AHB Error Interrupt Clear bit is set in the AHB Error Monitoring Configuration register (*).
..... SYSTEM CONTROL MODULE AHB Error Monitoring Configuration register Register bit assignment Bits Access Mnemonic Reset Description D31:20 N/A Reserved N/A N/A D19 * IE Not reset CPU instruction error An error was found on the CPU instruction access to external memory. The other fields in this register and the AHB Error Status 1 register are not valid if this bit is set. D18 * DE Not reset CPU data error An error was found on the CPU data access to external memory.
SYSTEM CONTROL MODULE Timer Master Control register Register 31 30 29 28 27 26 25 24 14 13 12 22 21 11 10 9 8 7 19 18 17 16 2 1 0 Reserved 6 5 4 3 SERDC Reserved Register bit assignment 20 EIC Reserved 15 23 Reserved Bits Access Mnemonic Reset Description D31:24 N/A Reserved N/A N/A D23 R/W EIC 0x0 AHB Error Interrupt Clear Write a 1, then a 0 to this register to clear the AHB error interrupt and to clear the AHB Error Detect Status 1 and AHB Error Dete
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SYSTEM CONTROL MODULE Timer 0–4 Control registers Bits Access Mnemonic Reset Description D09 R/W T9E 0x0 Timer 9 enable 0 1 D08 R/W T8E 0x0 Timer 8 enable 0 1 D07 R/W T7E 0x0 R/W T6E 0x0 R/W T5E 0x0 R/W T4E 0x0 R/W T3E 0x0 R/W T2E 0x0 R/W T1E 0x0 R/W T0E 0x0 Timer reset Timer enabled Timer 1 enable 0 1 D00 Timer reset Timer enabled Timer 2 enable 0 1 D01 Timer reset Timer enabled Timer 3 enable 0 1 D02 Timer reset Timer enabled Timer 4 enable 0 1 D03 Tim
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SYSTEM CONTROL MODULE Timer 5 Control register Bits Access Mnemonic Reset Description D05:04 R/W Timer mode 0x0 Timer mode 00 01 10 11 Internal timer or external event External low-level gated timer External high-level gated timer Concatenate the lower timer.
..... SYSTEM CONTROL MODULE Timer 5 Control register Register bit assignment Bits Access Mnemonic Reset Description D31:19 N/A Reserved N/A N/A D18 R/W Rel mode 0x0 Reload mode Initializes the timer and the reload value at terminal count. Reload mode is useful in quadrature decoder applications, as it allows the reload value to be half of he terminal count.
SYSTEM CONTROL MODULE Timer 6–9 Control registers Bits Access Mnemonic Reset Description D09:06 R/W TCS 0x0 Timer clock select 0000 0001 0010 0011 0100 0101 0110 0111 1000 1111 D05:04 R/W Timer mode 1 0x0 Timer mode 1 00 01 10 11 Internal timer or external event External low-level gated timer External high-level gated timer Concatenate the lower timer.
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SYSTEM CONTROL MODULE Timer 6–9 High registers Bits Access Mnemonic Reset Description D09:06 R/W TCS 0x0 Timer clock select 0000 0001 0010 0011 0100 0101 0110 0111 1000 1111 D05:04 R/W Timer mode 1 0x0 AHB clock x 2 (Not applicable if timer mode 2 is set to PWM mode (01)) AHB clock AHB clock / 2 AHB clock / 4 AHB clock / 8 AHB clock / 16 AHB clock / 32 AHB clock / 64 AHB clock / 128 External event Timer mode 1 00 Internal timer or external event 01 External low-level gated timer 10 External
..... SYSTEM CONTROL MODULE Timer 6–9 Low registers Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 High 15 14 13 12 11 10 9 8 High Register bit assignment Bits Access Mnemonic Reset Description D31:00 R/W High 0x0 The PWM output toggles high when the timer counter reaches this value. Timer 6–9 Low registers ..................................................................................
SYSTEM CONTROL MODULE Timer 6–9 High and Low Step registers Timer 6–9 High and Low Step registers .................................................................................. Addresses: A090 0098 / 009C / 00A0 / 00A4 The Timer 6–9 High and Low Step registers contain the high and low step registers for the enhanced PWM features available in timers 6 through 9.
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SYSTEM CONTROL MODULE Timer 0-9 Read and Capture register Register bit assignment Bits Access Mnemonic Reset Description D31:16 R/W Comp Rel Cnt 0x0 Timer Compare register or Timer Reload Bits 31:16 Count register An external toggle or pulse is generated each time the timer value matches this value. An interrupt is generated, if enabled. If configured for a 32-bit timer, bits 31:16 timer reload.
..... SYSTEM CONTROL MODULE Interrupt Vector Address Register Level 31–0 Interrupt Vector Address Register Level 31–0 ..................................................................................
SYSTEM CONTROL MODULE ISADDR register Register bit assignment Register [31:24] [23:16] [15:08] [07:00] A090 015C Int Config 24 Int Config 25 Int Config 26 Int Config 27 A090 0160 Int Config 28 Int Config 29 Int Config 30 Int Config 31 This is how the bits are assigned in each register, using data bits [07:00] as the example.
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SYSTEM CONTROL MODULE Interrupt Status Raw Interrupt Status Raw .................................................................................. Address: A090 016C The Interrupt Status Raw register shows all current interrupt requests.
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SYSTEM CONTROL MODULE Clock Configuration register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Watchdog Timer 15 14 13 12 11 10 9 8 7 Watchdog Timer Register bit assignment Bits Access Mnemonic Reset Description D31:00 R/W Watchdog timer 0x0 Watchdog timer A read to this register gives the current value of the watchdog timer, but will not change the contents. A write to the register changes the contents based on the write data value.
..... SYSTEM CONTROL MODULE Clock Configuration register Register bit assignment Bits Access Mnemonic Reset Description D31:29 R/W CSC 0x000 Clock scale control 000 Full speed (149.9136/74.9568) 001 Divide by 2 (74.9568/37.4784) 010 Divide by 4 (37.4784/18.7392) 011 Divide by 8 (18.7393/9.3693) 100 Divide by 16 (9.3693/4.6848) Determines the frequency of the system clock rates. The full speed rate is 150MHz for the CPU clock and 75MHz for the AHB clock.
SYSTEM CONTROL MODULE Module Reset register Bits Access Mnemonic Reset Description D13 R/W IO hub 0x1 IO hub 0 1 D12 R/W RTC 0x1 RTC 0 1 D11 R/W I2C 0x1 Clock disabled Clock enabled Clock disabled Clock enabled I2C 0 1 Clock disabled Clock enabled D10 N/A Reserved N/A N/A D09 R/W AES 0x0 AES 0 1 D08 R/W ADC 0x1 Clock disabled Clock enabled ADC 0 1 Clock disabled Clock enabled D07:06 N/A Reserved N/A Always write to 00 D05 R/W SPI 0x1 SPI 0 1 D04 R/W UART
..... SYSTEM CONTROL MODULE Module Reset register The Module Reset register resets each module on the AHB bus.
SYSTEM CONTROL MODULE Miscellaneous System Configuration and Status register Bits Access Mnemonic Reset Description D07:06 N/A Reserved N/A Always write to 00 D05 R/W SPI 0x1 SPI 0 1 D04 R/W UART D 0x1 UART D 0 1 D03 R/W UART C 0x1 R/W UART B 0x1 R/W UART A 0x1 R/W Eth MAC Module reset Module enabled UART A 0 1 D00 Module reset Module enabled UART B 0 1 D01 Module reset Module enabled UART C 0 1 D02 Module reset Module enabled 0x1 Module reset Module enabled Eth
..... SYSTEM CONTROL MODULE Miscellaneous System Configuration and Status register Register bit assignment Bits Access Mnemonic Reset Description D31:24 R REV 0x0 Revision Indicates the hardware identification and revision of the processor chip.
SYSTEM CONTROL MODULE PLL Configuration register PLL Configuration register .................................................................................. Address: A090 0188 The PLL Configuration register configures the PLL. A write to this register reconfigures and resets the PLL.
..... SYSTEM CONTROL MODULE Active Interrupt Level ID Status register Active Interrupt Level ID Status register .................................................................................. Address: A090 018C The Active Interrupt Level ID Status register is six bits in length, and shows the current active interrupt level ID.
SYSTEM CONTROL MODULE Power Management Register bit assignment Bits Access Mnemonic Reset Description D31 R/W Slp en 0x0 Deprecated Chip sleep enable This control bit is provided for backwards compatibility with software written for the NS9750 and NS9360 processors, and should not be used by new software. System software writes a 1 to this bit to stop the clock to the CPU.
..... SYSTEM CONTROL MODULE Power Management Bits Access Mnemonic Reset Description D20 R/W WakeIntClr 0x0 CPU wake interrupt clear Write a 1, followed by a 0 to clear the CPU wake interrupt.
SYSTEM CONTROL MODULE AHB Bus Activity Status Bits Access Mnemonic Reset Description D01 R/W UART A 0x0 UART A wakeup 0 1 D00 R/W Enet 0x0 Do not wake on character match Wake on character match Ethernet wakeup 0 Do not wake on Ethernet packet 1 Wake on Ethernet packet AHB Bus Activity Status ..................................................................................
..... SYSTEM CONTROL MODULE System Memory Chip Select 1 Dynamic Memory Base and Mask registers These control registers set the base and mask for system memory chip select 0, with a minimum size of 4K. The powerup default settings produce a memory range of 0x0000 0000 — 0x0FFF FFFF.
SYSTEM CONTROL MODULE System Memory Chip Select 2 Dynamic Memory Base and Mask registers Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 1 base (CS1B) 15 14 13 12 11 10 9 8 7 Chip select 1 base (CS1B) 31 30 29 6 Reserved 28 27 26 25 24 23 22 Chip select 1 mask (CS1M) 15 14 13 12 11 10 9 8 7 Chip select 1 mask (CS1M) Register bit assignment 6 Reserved Bits Access Mnemonic
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SYSTEM CONTROL MODULE System Memory Chip Select 0 Static Memory Base and Mask registers Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 3 base (CS3B) 15 14 13 12 11 10 9 8 7 Chip select 3 base (CS3B) 31 30 29 6 Reserved 28 27 26 25 24 23 22 Chip select 3 mask (CS3M) 15 14 13 12 11 10 9 8 7 Chip select 3 mask (CS3M) Register bit assignment 6 Reserved Bits Access Mnemonic
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SYSTEM CONTROL MODULE System Memory Chip Select 2 Static Memory Base and Mask registers Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 1 base (CS1B) 15 14 13 12 11 10 9 8 7 Chip select 1 base (CS1B) 31 30 29 6 Reserved 28 27 26 25 24 23 22 Chip select 1 mask (CS1M) 15 14 13 12 11 10 9 8 7 Chip select 1 mask (CS1M) Register bit assignment 6 Reserved Bits Access Mnemonic
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SYSTEM CONTROL MODULE Gen ID register Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 3 base (CS3B) 15 14 13 12 11 10 9 8 7 Chip select 3 base (CS3B) 31 30 29 6 Reserved 28 27 26 25 24 23 22 Chip select 3 mask (CS3M) 15 14 13 12 11 10 9 8 7 Chip select 3 mask (CS3M) Register bit assignment 6 Reserved Bits Access Mnemonic Reset Description D31:12 R/W CS3B 0x70000 C
..... SYSTEM CONTROL MODULE External Interrupt 0–3 Control register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 Reserved Register bit assignment GENID Bits Access Mnemonic Reset Description D31:11 N/A Reserved N/A N/A D10:00 R GENID HW strap addr[19:09] General Purpose ID register External Interrupt 0–3 Control register ...........................................................................
SYSTEM CONTROL MODULE RTC Module Control register Bits Access Mnemonic Reset Description D01 R/W PLTY 0x0 Polarity 0 If level-sensitive, the input source is active high. 1 If edge-sensitive, generate an interrupt on the rising edge of the external interrupt. If level-sensitive, the input source is active low. The level is inverted before sending to the interrupt controller. If edge-sensitive, generate an interrupt on the falling edge of the external interrupt.
..... SYSTEM CONTROL MODULE RTC Module Control register Bits Access Mnemonic Reset Description D03 R Rdy int 0x0 RTC clock ready interrupt status 0 1 RTC clock ready interrupt not asserted RTC clock ready interrupt asserted Note: D02 R Int stat 0x0 RTC module interrupt status 0 1 RTC module interrupt not asserted RTC module interrupt asserted Note: D01 R/W Standby mode 0x0 The RTC clock ready and RTC module interrupts are ORed together to the interrupt controller.
SYSTEM CONTROL MODULE RTC Module Control register 202 Hardware Reference NS9215
Memory Controller C H A P T E R 5 T he Multiport Memory Controller is an AMBA-compliant system-on-chip (SoC) peripheral that connects to the Advanced High-performance Bus (AHB). The remainder of this chapter refers to this controller as the memory controller.
MEMORY CONTROLLER Low-power operation Power-saving modes that dynamically control SDRAM clk_en. Dynamic memory self-refresh mode supported by a power management unit (PMU) interface or by software. Controller supports 2K, 4K, and 8K row address synchronous memory parts; that is, typical 512 MB, 256 MB, and 16 Mb parts with 8, 16, or 32 DQ bits per device. A separate AHB interface to program the memory controller.
..... MEMORY CONTROLLER Memory map Memory map .................................................................................. The memory controller provides hardware support for booting from external nonvolatile memory. During booting, the nonvolatile memory must be located at address 0x00000000 in memory. When the system is booted, the SRAM or SDRAM memory can be remapped to address 0x00000000 by modifying the address map in the AHB decoder.
MEMORY CONTROLLER Memory map Example: Boot from flash, SDRAM remapped after boot 2 When the power-on reset (reset_n) goes inactive, the processor starts booting from 0x00000000 in memory. 3 The software programs the optimum delay values in the flash memory so the boot code can run at full speed. 4 The code branches to chip select 1 so the code can continue executing from the non-remapped memory location. 5 The appropriate values are programmed into the memory controller to configure chip select 0.
..... MEMORY CONTROLLER Static memory controller 2 When the power-on reset (reset_n) goes inactive, the processor starts booting from 0x00000000 in memory. 3 The software programs the optimum delay values in flash memory so the boot code can run at full speed. 4 The code branches to chip select 1 so the code can continue executing from the non-remapped memory location.
MEMORY CONTROLLER Static memory controller Notes: Buffering enables the transaction order to be rearranged to improve memory performance. If the transaction order is important, the buffers must be disabled. Extended wait and page mode cannot be enabled at the same time. Write protection Each static memory chip select can be configured for write-protection.
..... MEMORY CONTROLLER Static memory initialization time critical services, such as interrupt latency and low latency devices; for example, video controllers. Memory mapped peripherals Some systems use external peripherals that can be accessed using the static memory interface. Because of the way many of these peripherals function, the read and write transfers to them must not be buffered. The buffer must therefore be disabled. Static memory initialization ............................................
MEMORY CONTROLLER Static memory read control “Static Memory Extended Wait register” on page 247 (StaticExtendedWait) The number of cycles in which an AMBA transfer completes is controlled by two additional factors: Access width External memory width Programmable enable Each bank of the memory controller has a programmable enable for the extended wait (EW).
..... MEMORY CONTROLLER Static memory read: Timing and parameters Static memory read: Timing and parameters .................................................................................. This section shows static memory read timing diagrams and parameters. External memory read transfer with zero wait states This diagram shows an external memory read transfer with the minimum zero wait states (WAITRD=0).
MEMORY CONTROLLER Static memory read: Timing and parameters External memory read transfer with two output enable delay states Timing parameter Value WAITEN N/A WAITTURN N/A This diagram shows an external memory read transfer with two output enable delay states (WAITOEN=2). Seven AHB cycles are required for the transfer, five for the standard read and an additional two because of the output delay states added.
..... MEMORY CONTROLLER Static memory read: Timing and parameters Burst of zero wait states with fixed length Timing parameter Value WAITRD 0 WAITOEN 0 WAITPAGE N/A WAITWR N/A WAITWEN N/A WAITTURN N/A This diagram shows a burst of zero wait state reads with the length specified. Because the length of the burst is known, the chip select can be held asserted during the whole burst and generate the external transfers before the current AHB transfer has completed.
MEMORY CONTROLLER Asynchronous page mode read clk_out addr A A+4 data A+8 D(A) D(A+4) cs[n] st_oe_n Timing parameter Value WAITRD 2 WAITOEN 0 WAITPAGE N/A WAITWR N/A WAITWEN N/A WAITTURN N/A Asynchronous page mode read .................................................................................. The memory controller supports asynchronous page mode read of up to four memory transfers by updating address bits addr[1] and addr[0].
..... MEMORY CONTROLLER Asynchronous page mode read: Timing and parameters clk_out addr A A+4 data D(A) D(A+4) cs[n] st_oe_n External memory 32-bit burst read from 8-bit memory A+8 Timing parameter Value WAITRD 2 WAITOEN 0 WAITPAGE 1 WAITWR N/A WAITWEN N/A WAITTURN N/A D(A+8) This diagram shows a 32-bit read from an 8-bit page mode ROM device, causing four burst reads to be performed.
MEMORY CONTROLLER Static memory write control Static memory write control .................................................................................. Write enable programming delay The delay between the assertion of the chip select and the write enable is programmable from 1 to 16 cycles using the WAITWEN bits of the Static Memory Write Enable Delay (StaticWaitWen[3:0]) registers. The delay reduces the power consumption for memories.
..... MEMORY CONTROLLER Static memory Write: Timing and parameters External memory write transfer with two wait states Timing parameters Value WAITRD N/A WAITOEN N/A WAITPAGE N/A WAITWR 0 WAITWEN 0 WAITTURN N/A This diagram shows a single external memory write transfer with two wait states (WAITWR=2). One AHB wait state is added.
MEMORY CONTROLLER Static memory Write: Timing and parameters Two external memory write transfers with zero wait states Timing parameters Value WAITRD N/A WAITOEN N/A WAITPAGE N/A WAITWR 2 WAITWEN 2 WAITTURN N/A This diagram shows two external memory write transfers with zero wait states (WAITWR=0). Four AHB wait states are added to the second write, because this write can be started only when the first write has completed.
..... MEMORY CONTROLLER Bus turnaround Bus turnaround .................................................................................. The memory controller can be configured for each memory bank to use external bus turnaround cycles between read and write memory accesses. The WAITTURN field can be programmed for 1 to 16 turnaround wait states, to avoid bus contention on the external memory databus.
MEMORY CONTROLLER Bus turnaround: Timing and parameters Write followed by a read with no turnaround This diagram shows a zero wait write followed by a zero wait read with default turnaround between the transfers of one cycle. Three wait states are added to the write transfer; five wait states are added to the read transfer. The five AHB arbitration cycles for the read transfer include two wait states to allow the previous write access to complete and the three standard wait states for the read transfer.
..... MEMORY CONTROLLER Byte lane control Timing parameters Value WAITRD 0 WAITOEN 0 WAITPAGE N/A WAITWR 0 WAITWEN 0 WAITTURN 2 Byte lane control ..................................................................................
MEMORY CONTROLLER Address connectivity Address connectivity .................................................................................. Memory banks constructed from 8-bit or non-bytepartitioned memory devices For memory banks constructed from 8-bit or non-byte-partitioned memory devices, it is important that the byte lane state (PB) bit is cleared to 0 within the respective memory bank control register.
..... MEMORY CONTROLLER Address connectivity Memory banks constructed from 16-or 32-bit memory devices For memory banks constructed from 16- or 32-bit memory devices, it is important that the byte lane select (PB) bit is set to 1 within the respective memory bank control register. This asserts all data_mask[3:0] lines low during a read access as, during a read, all device bytes must be selected to avoid undriven byte lanes on the read data value.
MEMORY CONTROLLER Address connectivity addr[22:2] addr[22:0] datat[31:0] A[20:0] cs[0] CE_n st_oe_n OE_n Q[31:0] data[31:0] 2Mx32 ROM addr[11:2] data[31:16] A[15:0] cs[1] IO[15:0] CE_n OE_n st_we_n WE_n UB_n LB_n addr[17:2] data[15:0] A[15:0] IO[15:0] CE_n OE_n WE_n UB_n LB_n 64Kx16 SRAM addr[18:2] data[31:24] A[16:0] IO[7:0] CE_n cs[2] OE_n WE_n data_mask[3] addr[18:2] data[23:16] A[16:0] IO[7:0] CE_n OE_n WE_n data_mask[2] addr[18:2] data[15:8] A[16:0] IO[7:0] CE_n OE_n WE_
..... MEMORY CONTROLLER Dynamic memory controller Dynamic memory controller .................................................................................. Write protection Each dynamic memory chip select can be configured for write-protection by setting the appropriate bit in the write protect (P) field on the Dynamic Memory Configuration register. If a write access is performed to a write-protected memory bank, a bus error is generated.
MEMORY CONTROLLER SDRAM Initialization 10 Set the SDRAMInit value in the Dynamic Control register to 01 — Issue SDRAM Mode command. 11 Program the SDRAM memory 10-bit mode register.
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MEMORY CONTROLLER SDRAM address and data bus interconnect Left-shift value table: 16-bit wide data bus SDRAM (BRC) Device size Configuration Load Mode register left shift 16M 1 x 1M x 16 9 2 x 2M x 8 10 1 x 4M x 16 9 2 x 8M x 8 10 1 x 8M x 16 10 2 x 16M x 8 11 1 x 16M x 16 10 2 x 32M x 8 11 1 x 32M x 16 11 2 x 64M x 8 12 64M 128 256M 512M SDRAM address and data bus interconnect ..................................................................................
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MEMORY CONTROLLER Registers Signal 16M device SDRAM signal 64M device SDRAM signal 128M device SDRAM signal 256M device SDRAM signal 512M device SDRAM signal addr[21] BA0 BA0 BA0 BA0 addr[22] BA1 BA1 BA1 BA1 ap10 A10/AP A10/AP A10/AP A10/AP data[31:16] D[15:0] D[15:0] D[15:0] D[15:0] addr[15] addr[16] addr[17] addr[18] addr[19] addr[20] BA * A12 used only in 2 x 16M x 8 configurations Registers ..................................................................................
..... MEMORY CONTROLLER Registers www.digiembedded.
MEMORY CONTROLLER Control register Reset values Address Register Description A070 0240 StaticConfig2 Static Memory Configuration Register 2 A070 0244 StaticWaitWen2 Static Memory Write Enable Delay 2 A070 0248 StaticWaitOen2 Static Memory Output Enable Delay 2 A070 024C StaticWaitRd2 Static Memory Read Delay 2 A070 0250 StaticWaitPage2 Static Memory Page Mode Read Delay 2 A070 0254 StaticWaitWr2 Static Memory Write Delay 2 A070 0258 StaticWaitTurn2 Static Memory Turn Round Delay 2
..... MEMORY CONTROLLER Control register Register bit assignment Bits Access Mnemonic Description D31:03 N/A Reserved N/A (do not modify) D02 R/W LPM Low-power mode 0 Normal mode (reset value on reset_n) 1 Low-power mode Indicates normal or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit or by poweron reset.
MEMORY CONTROLLER Status register Status register .................................................................................. Address: A070 0004 The Status register provides memory controller status information.
..... MEMORY CONTROLLER Dynamic Memory Control register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 Reserved Register bit assignment END Bits Access Mnemonic Description D31:01 N/A Reserved N/A (do not modify) D00 R/W END Endian mode 0 Little endian mode 1 Big endian mode The value of the endian bit on power-on reset (reset_n) is determined by the gpio_a[3] signal.
MEMORY CONTROLLER Dynamic Memory Refresh Timer register Register bit assignment Bits Access Mnemonic Description D31:15 N/A Reserved N/A (do not modify) D14 R/W nRP Sync/Flash reset/power down signal (dy_pwr_n) 0 1 dy_pwr_n signal low (reset value on reset_n) Set dy_pwr_n signal high D13 R/W Not used Always write to 0.
..... MEMORY CONTROLLER Dynamic Memory Read Configuration register The Dynamic Memory Refresh Timer register configures dynamic memory operation. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.These bits can, however, be changed during normal operation if necessary.
MEMORY CONTROLLER Dynamic Memory Precharge Command Period register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 RD Reserved Register bit assignment Bits Access Mnemonic Description D31:02 N/A Reserved N/A (do not modify) D01:00 R/W RD Read data strategy 00 01 10 11 Reserved. Command delayed strategy, using CLKDELAY (command delayed, clock out not delayed).
..... MEMORY CONTROLLER Dynamic Memory Active to Precharge Command Period register Register bit assignment Bits Access Mnemonic Description D31:04 N/A Reserved N/A (do not modify) D03:00 R/W RP Precharge command period (tRP) 0x0–0xE n+1 clock cycles, where the delay is in clk_out cycles. 0xF 16 clock cycles (reset value on reset_n) Dynamic Memory Active to Precharge Command Period register ..................................................................................
MEMORY CONTROLLER Dynamic Memory Self-refresh Exit Time register Dynamic Memory Self-refresh Exit Time register .................................................................................. Address: A070 0038 The Dynamic Memory Self-refresh Exit Time register allows you to program the selfrefresh exit time, tSREX. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions.
..... MEMORY CONTROLLER Dynamic Memory Data-in to Active Command Time register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 Reserved Register bit assignment APR Bits Access Mnemonic Description D31:04 N/A Reserved N/A (do not modify) D03:00 R/W APR Last-data-out to active command time (tAPR) 0x0–0xE n+1 clock cycles, where the delay is in clk_out cycles.
MEMORY CONTROLLER Dynamic Memory Write Recovery Time register Register bit assignment Bits Access Mnemonic Description D31:04 N/A Reserved N/A (do not modify) D03:00 R/W DAL Data-in to active command (tDAL or tAPW) 0x0–0xE n+1 clock cycles, where the delay is in clk_out cycles. 0xF 15 clock cycles (reset value on reset_n) Dynamic Memory Write Recovery Time register ..................................................................................
..... MEMORY CONTROLLER Dynamic Memory Active to Active Command Period register Dynamic Memory Active to Active Command Period register .................................................................................. Address: A070 0048 The Dynamic Memory Active to Active Command Period register allows you to program the active to active command period, tRC. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions.
MEMORY CONTROLLER Dynamic Memory Exit Self-refresh register Note: The Dynamic Memory Auto Refresh Period register is used for all four dynamic memory chip selects. The worst case value for all chip selects must be programmed.
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MEMORY CONTROLLER Dynamic Memory Load Mode register to Active Command Time register Register bit assignment Bits Access Mnemonic Description D31:04 N/A Reserved N/A (do not modify) D03:00 R/W RRD Active Bank A to Active Bank B 0x0–0xE n+1 clock cycles, where the delay is in clk_out cycles 0xF 16 clock cycles (reset on reset_n) Dynamic Memory Load Mode register to Active Command Time register ..................................................................................
..... MEMORY CONTROLLER Static Memory Extended Wait register Static Memory Extended Wait register ..................................................................................
MEMORY CONTROLLER Dynamic Memory Configuration 0–3 registers Use the Dynamic Memory Configuration 0–3 registers to program the configuration information for the relevant dynamic memory chip select. These registers are usually modified only during system initialization.
..... MEMORY CONTROLLER Dynamic Memory Configuration 0–3 registers Address mapping for the Dynamic Memory Configuration registers The next table shows address mapping for the Dynamic Memory Configuration 0-3 registers. Address mappings that are not shown in the table are reserved.
MEMORY CONTROLLER Dynamic Memory RAS and CAS Delay 0–3 registers [14] [12] [11:9] [8:7] Description 1 0 011 01 256 Mb (16Mx16), 4 banks, row length=13, column length=9 1 0 011 10 256 Mb (8Mx32), 4 banks, row length=13, column length=8 1 0 100 00 512 Mb (64Mx8), 4 banks, row length=13, column length=11 1 0 100 01 512 Mb (32Mx16), 4 banks, row length=13, column length=10 32-bit extended bus low-power SDRAM address mapping (bank, row, column) Chip select and memory devices Chip sel
..... MEMORY CONTROLLER StaticMemory Configuration 0–3 registers The Dynamic Memory RAS and CAS Delay 0–3 registers allow you to program the RAS and CAS latencies for the relevant dynamic memory. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter lowpower or disabled mode.
MEMORY CONTROLLER StaticMemory Configuration 0–3 registers Register 31 30 29 28 27 26 25 24 23 22 21 Reserved 15 14 13 12 11 10 9 Reserved Register bit assignment 8 7 6 EW PB PC Bits Access Mnemonic Description D31:21 N/A Reserved N/A (do not modify) D20 R/W PSMC Write protect 0 1 D19 R/W BSMC 5 20 19 PSMC BSMC 4 3 Reserved PM 18 17 16 Reserved 2 BMODE 1 0 MW Writes not protected (reset value on reset_n) Write protected Buffer enable 0 1 Write bu
..... MEMORY CONTROLLER StaticMemory Configuration 0–3 registers Bits Access Mnemonic Description D07 R/W PB Byte lane state 0 For reads, all bits in byte_lane[3:0] are high. 1 For writes, the respective active bits in byte_lane[3:0] are low (reset value for chip select 0, 2, and 3 on reset_n). For reads, the respective active bits in byte_lane[3:0] are low. For writes, the respective active bits in byte_lane[3:0] are low. Note: Setting this bit to 0 disables the write enable signal.
MEMORY CONTROLLER StaticMemory Write Enable Delay 0–3 registers Bits Access Mnemonic Description D02 R/W BMODE Burst mode Allows the static output enable signal to toggle during bursts.
..... MEMORY CONTROLLER Static Memory Output Enable Delay 0–3 registers Register bit assignment Bits Access Mnemonic Description D31:04 N/A Reserved N/A (do not modify) D03:00 R/W WWEN Wait write enable (WAITWEN) 0000 One clk_out cycle delay between assertion of chip select and write enable (reset value on reset_n). 0001–1111 (n+1) clk_out cycle delay, where the delay is (WAITWEN+1) x tclk_out Delay from chip select assertion to write enable.
MEMORY CONTROLLER Static Memory Read Delay 0–3 registers Static Memory Read Delay 0–3 registers .................................................................................. Address: A070 020C / 022C / 024C / 026C The Static Memory Read Delay 0–3 registers allow you to program the delay from the chip select to the read access. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions.
..... MEMORY CONTROLLER Static Memory Write Delay 0–3 registers modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.
MEMORY CONTROLLER StaticMemory Turn Round Delay 0–3 registers Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 Reserved Register bit assignment WTWR Bits Access Mnemonic Description D31:05 N/A Reserved N/A (do not modify) D04:00 R/W WTWR Write wait states (WAITWR) 00000–11110 (n+2) clk_out cycle write access time.
..... MEMORY CONTROLLER StaticMemory Turn Round Delay 0–3 registers Register bit assignment Bits Access Mnemonic Description D31:04 N/A Reserved N/A (do not modify) D03:00 R/W WTTN Bus turnaround cycles (WAITTURN) 00000–11110 (n+1) clk_out turnaround cycles, where bus turnaround time is (WAITTURN+1) x tclk_out 1111 16 clk_out turnaround cycles (reset value on reset_n).
MEMORY CONTROLLER StaticMemory Turn Round Delay 0–3 registers 260 Hardware Reference NS9215
..... ETHERNET COMMUNICATION MODULE Ethernet Communication Module C H A P T E R 6 T he Ethernet Communication module consists of an Ethernet Media Access Controller (MAC) and Ethernet front-end module. The Ethernet MAC interfaces to an external PHY through the industry-standard interface: Media Independent Interface (MII). The Ethernet front-end module provides all of the control functions to the MAC.
ETHERNET COMMUNICATION MODULE Ethernet MAC Ethernet communications module Ethernet PHY TX RX MGMT Hash Table Host Interface Flow Control Receive Transmit Ethernet MAC Ethernet Front End SYSTEM BUS Ethernet MAC .................................................................................. The Ethernet MAC includes a full function 10/100 Mbps Media Access Controller (MAC), station address filtering logic (SAL), statistic collection module (STAT), and MII.
..... ETHERNET COMMUNICATION MODULE Ethernet MAC MAC module block diagram MAC module features Feature Description MAC Core 10/100 megabit Media Access Controller Performs the CSMA/CD function. MCS: MAC control sublayer TFUN: Transmit function RFUN: Receive function HOST Host interface Provides an interface for control and configuration. CLK & Reset Clocks & resets Provides a central location for clock trees and reset logic. MIIM MII management Provides control/status path to MII PHYs.
ETHERNET COMMUNICATION MODULE Station address logic (SAL) Feature Description SAL Station address logic Performs destination address filtering. MII Media Independent Interface Provides the interface from the MAC core to a PHY that supports the MII (as described in the IEEE 802.3 standard). PHY interface mappings This table shows how the different PHY interfaces are mapped to the external IO.
..... ETHERNET COMMUNICATION MODULE Statistics module module. The filtering options, listed next, are programmed in the Station Address Filter register (see page 301). Accept frames to destination address programmed in the SA1, SA2, and SA3 registers (Station Address registers, beginning on page 300) Accept all frames Accept all multicast frames Accept all multicast frames using HT1 and HT2 registers.
ETHERNET COMMUNICATION MODULE Ethernet front-end module The counters support a clear on read capability that is enabled when AUTOZ is set to 1 in the Ethernet General Control Register #2. Ethernet front-end module ..................................................................................
..... ETHERNET COMMUNICATION MODULE Receive packet processor The 2K byte RX_FIFO allows the entire Ethernet frame to be buffered while the receive byte count is analyzed. The receive byte count is analyzed by the receive packet processor to select the optimum-sized buffer for transferring the received frame to system memory. The processor can use one of four different-sized receive buffers in system memory.
ETHERNET COMMUNICATION MODULE Receive packet processor Transferring a frame to system memory The RX_RD logic manages the transfer of a frame in the RX_FIFO to system memory. The transfer is enabled by setting the ERXDMA (enable receive DMA) bit in Ethernet General Control Register #1. Transferring a frame in the receive FIFO to system memory begins when the RX_WR logic notifies the RX_RD logic that a good frame is in the receive FIFO.
..... ETHERNET COMMUNICATION MODULE Transmit packet processor Receive buffer descriptor field definitions Field Description W WRAP bit, which, when set, tells the RX_RD logic that this is the last buffer descriptor in the ring. In this situation, the next buffer descriptor is found using the appropriate Buffer Descriptor Pointer register. When the WRAP bit is not set, the next buffer descriptor is found using an offset of 0x10 from the current buffer descriptor pointer.
ETHERNET COMMUNICATION MODULE Transmit packet processor reside in different buffers in system memory, several buffer descriptors can be used to transfer the frame. Transmit buffer descriptor format All buffer descriptors (that is, up to 64) are found in a local TX buffer descriptor RAM. This is the transmit buffer descriptor format.
..... ETHERNET COMMUNICATION MODULE Transmit packet processor Field Description F When set, indicates the buffer is full. The TX_WR logic clears this bit after emptying a buffer. The system software sets this bit as required, to signal that the buffer is ready for transmission. If the TX_WR logic detects that this bit is not set when the buffer descriptor is read, it does one of two things: If a frame is not in progress, the TX_WR logic sets the TXIDLE bit in the Ethernet Interrupt Status register.
ETHERNET COMMUNICATION MODULE Transmit packet processor The TX_WR logic examines the status received from the MAC after it has transmitted the frame. Frame transmitted successfully If the frame was transmitted successfully, the TX_WR logic sets TXDONE (frame transmission complete) in the Ethernet Interrupt Status register and reads the next buffer descriptor. If a new frame is available (that is, the F bit is set), the TX_WR starts transferring the frame.
..... ETHERNET COMMUNICATION MODULE Ethernet slave interface – A packet consisting of multiple, linked buffer descriptors does not have the F bit set in any of the non-first buffer descriptors. When an underrun occurs, it is also possible for the Ethernet transmitter to send out a corrupted packet with a good Ethernet CRC if the MAC is configured to add the CRC to the frame (that is, CRCEN in MAC Configuration Register #2 is set to 1). Ethernet slave interface ........................................
ETHERNET COMMUNICATION MODULE Resets Status bits Interrupt condition Description Interrupt No receive buffers No buffer is available for this frame because all 4 buffer rings are RX disabled, full, or no available buffer is big enough for the frame. Receive buffers full No buffer is available for this frame because all 4 buffers are disabled or full. RX RX buffer ready Frame available in RX_FIFO. (Used for diagnostics.
..... ETHERNET COMMUNICATION MODULE Multicast address filtering Bit field Register Active state Default state Modules reset RPETFUN MAC1 1 0 MAC TX logic MIIM MII Management Configuration register 1 0 MAC MIIM logic Multicast address filtering .................................................................................. The RX-WR logic contains a programmable 8-entry multicast address filter that provides more restrictive filtering than that available in the MAC using the SAL.
ETHERNET COMMUNICATION MODULE Clock synchronization Multicast address filtering example 2 To accept multicast packets with destination addresses in the range of 0x01_00_5E_00_00_00 to 0x01_00_5E_00_00_0f using entry 4, the registers are set as shown: Register Value Function MFILTEN 0x10 Enable entry 4 MFILTL4 0x5E_00_00_00 Lower 32 bits of multicast address MFILTH4 0x01_00 Upper 16 bits of multicast address MCMSKL4 0xFFFF_FFF0 Include only bits [31:04] of the lower 32 bits of the multicast
..... ETHERNET COMMUNICATION MODULE Ethernet Control and Status registers Ethernet Control and Status registers .................................................................................. All configuration registers must be accessed as 32-bit words and as single accesses only. Bursting is not allowed.
ETHERNET COMMUNICATION MODULE Ethernet Control and Status registers 278 Address Register Description A060 0A0C RXDPTR RX_D Buffer Descriptor Pointer register A060 0A10 EINTR Ethernet Interrupt Status register A060 0A14 EINTREN Ethernet Interrupt Enable register A060 0A18 TXPTR TX Buffer Descriptor Pointer register A060 0A1C TXRPTR TX Recover Buffer Descriptor Pointer register A060 0A20 TXERBD TX Error Buffer Descriptor Pointer register A060 0A24 TXSPTR TX Stall Buffer Descriptor Po
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ETHERNET COMMUNICATION MODULE Ethernet General Control Register #1 Register bit assignment Bits Access Mnemonic Reset Description D31 R/W ERX 0 Enable RX packet processing 0 Reset RX 1 Enable RX Used as a soft reset for the RX. When cleared, resets all logic in the RX and flushes the FIFO. The ERX bit must be set active high to allow data to be received from the MAC receiver.
..... ETHERNET COMMUNICATION MODULE Ethernet General Control Register #1 Bits Access Mnemonic Reset Description D22 R/W ETXDMA 0 Enable transmit DMA 0 Disable transmit DMA data request (use to stall transmitter) 1 Enable transmit DMA data request Must be set active high to allow the transmit packet processor to issue transmit data requests to the AHB interface. Set this bit to 0 to temporarily stall frame transmission, which always stalls at the completion of the current frame.
ETHERNET COMMUNICATION MODULE Ethernet General Control Register #2 Bits Access Mnemonic Reset Description D10 R/W RXALIGN 0 Align RX data 0 Standard receive format. The data block immediately follows the 14-byte header block. The receiver inserts a 2-byte padding between the 14byte header and the data block, causing longword alignment for both the header and data blocks. 1 D09 R/W MAC_HRST 1 MAC host interface soft reset 0 Restore MAC, STAT, SAL, RX_WR, and TX_RD to normal operation.
..... ETHERNET COMMUNICATION MODULE Ethernet General Status register Register bit assignment Bits Access Mnemonic Reset Description D31:08 R/W Not used 0 Always write as 0. D07 R/W TCLER 0 Clear transmit error 0 1 transition: Clear transmit error.
ETHERNET COMMUNICATION MODULE Ethernet Transmit Status register Register 31 30 29 28 27 26 25 24 23 22 21 Reserved 15 14 13 12 11 10 20 19 RX INIT 9 8 7 6 5 4 18 17 16 Reserved 3 2 1 0 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:21 N/A Reserved N/A N/A D20 R/C RXINIT 0x0 RX initialization complete Set when the RX_RD logic has completed the initialization of the local buffer descriptor registers requested when ERXINIT in Ethe
..... ETHERNET COMMUNICATION MODULE Ethernet Transmit Status register Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15 R TXOK 0x0 Frame transmitted OK When set, indicates that the frame has been delivered to and emptied from the transmit FIFO without problems. D14 R TXBR 0x0 Broadcast frame transmitted When set, indicates the frame’s destination address was a broadcast address.
ETHERNET COMMUNICATION MODULE Ethernet Receive Status register Bits Access Mnemonic Reset Description D08 R TXAJ 0x0 TX abort — jumbo When set, indicates that the frame’s length exceeded the value set in the Maximum Frame register. TXAJ is set only if the HUGE bit in MAC Configuration Register #2 is set to 0. Jumbo frames result in the TX buffer descriptor buffer length field being set to 0x000. If the HUGE bit is set to 0, the frame is truncated.
..... ETHERNET COMMUNICATION MODULE Ethernet Receive Status register Register 31 30 29 28 27 26 25 24 23 22 Reserved Register bit assignment 21 20 19 18 17 16 4 3 2 1 0 RXSIZE 15 14 13 12 11 10 9 RXCE RXDV RXOK RXBR RXMC Rsvd RXDR 8 7 Reserved 6 5 RXSHT Reserved Bits Access Mnemonic Reset Description D31:27 N/A Reserved N/A N/A D26:16 R RXSIZE 0x000 Receive frame size in bytes Length of the received frame, in bytes.
ETHERNET COMMUNICATION MODULE MAC Configuration Register #1 Bits Access Mnemonic Reset Description D06 R RXSHT 0x0 Receive frame is too short Set when the frame’s length is less than 64 bytes. Short frames are accepted only when the ERXSHT bit is set to 1 in Ethernet General Control Register #1. D05:00 N/A Reserved N/A N/A MAC Configuration Register #1 ..................................................................................
..... ETHERNET COMMUNICATION MODULE MAC Configuration Register #2 Bits Access Mnemonic Reset Description D04 R/W LOOPBK 0 Internal loopback Set this bit to 1 to cause the MAC transmit interface to be internally looped back to the MAC receive interface. Clearing this bit results in normal operation. D03:01 R/W Not used 0 Always write as 0. D00 R/W RXEN 0 Receive enable Set this bit to 1 to allow the MAC receiver to receive frames. MAC Configuration Register #2 ........................
ETHERNET COMMUNICATION MODULE MAC Configuration Register #2 Bits Access Mnemonic Reset Definition D09 R/W LONGP 0 Long preamble enforcement 0 1 D08 R/W PUREP 0 Pure preamble enforcement 0 1 D07 R/W AUTOP 0 Allows any length preamble (as defined in the 802.3u standard). The MAC allows only receive frames that contain preamble fields less than 12 bytes in length.
..... ETHERNET COMMUNICATION MODULE Back-to-Back Inter-Packet-Gap register Bits Access Mnemonic Reset Definition D01 R/W Not used 0 Always write as 0. D00 R/W FULLD 0 Full-duplex 0 1 PAD operation table for transmit frames The MAC operates in half-duplex mode. The MAC operates in full-duplex mode.
ETHERNET COMMUNICATION MODULE Non Back-to-Back Inter-Packet-Gap register Register bit assignment Bits Access Mnemonic Reset Description D31:07 N/A Reserved N/A N/A D06:00 R/W IPGT 0x00 Back-to-back inter-packet-gap Programmable field that indicates the nibble time offset of the minimum period between the end of any transmitted frame to the beginning of the next frame. Full-duplex mode Register value should be the appropriate period in nibble times minus 3.
..... ETHERNET COMMUNICATION MODULE Collision Window/Retry register Register bit assignment Bits Access Mnemonic Reset Description D31:15 N/A Reserved N/A N/A D14:08 R/W IPGR1 0x00 Non back-to-back inter-packet-gap part 1 Programmable field indicating optional carrierSense window (referenced in IEEE 8.2.3/4.2.3.2.1). If carrier is detected during the timing of IPGR1, the MAC defers to carrier.
ETHERNET COMMUNICATION MODULE Maximum Frame register Register bit assignment Bits Access Mnemonic Reset Description D31:14 N/A Reserved N/A N/A D13:08 R/W CWIN 0x37 Collision window Programmable field indicating the slot time or collision window during which collisions occur in properly configured networks. Because the collision window starts at the beginning of transmissions, the preamble and SFD (start-of-frame delimiter) are included.
..... ETHERNET COMMUNICATION MODULE MII Management Configuration register Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15:00 R/W MAXF 0x0600 Maximum frame length Default value of 0x600 represents a maximum receive frame of 1536 octets. An untagged maximum-size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. To use a shorter maximum length restriction, program this field accordingly.
ETHERNET COMMUNICATION MODULE MII Management Command register Bits Access Mnemonic Reset Description D04:02 R/W CLKS 0x0 Clock select Used by the clock divide logic in creating the MII management clock, which (per the IEEE 802.3u standard) can be no faster than 2.5 MHz. Note: Some PHYs support clock rates up to 12.5 MHz. The AHB bus clock is used as the input to the clock divide logic. See the “Clocks field settings” table for settings that can be used with AHB clock (hclk) frequencies.
..... ETHERNET COMMUNICATION MODULE MII Management Address register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SCAN READ Reserved 15 14 13 12 11 10 9 8 7 Reserved Register bit assignment If both SCAN and READ are set, SCAN takes precedence.
ETHERNET COMMUNICATION MODULE MII Management Write Data register Register bit assignment Bits Access Mnemonic Reset Description D31:13 N/A Reserved N/A N/A D12:08 R/W DADR 0x00 MII PHY device address Represents the 5-bit PHY device address field for management cycles. Up to 32 different PHY devices can be addressed. D07:05 N/A Reserved N/A N/A D04:00 R/W RADR 0x00 MII PHY register address Represents the 5-bit PHY register address field for management cycles.
..... ETHERNET COMMUNICATION MODULE MII Management Indicators register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 MRDD Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15:00 R MRDD 0x0000 MII read data Read data is obtained by reading from this register after an MII Management read cycle.
ETHERNET COMMUNICATION MODULE Station Address registers Bits Access Mnemonic Reset Description D02 R NVALID 0 Read data not valid When set to 1, indicates that the MII Management read cycle has not completed and the read data is not yet valid. Also indicates that SCAN READ is not valid for automatic scan reads. D01 R SCAN 0 Automatically scan for read data in progress When set to 1, indicates that continuous MII Management scanning read operations are in progress.
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ETHERNET COMMUNICATION MODULE RegisterHash Tables Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 PRO PRM PRA BROAD Reserved 15 14 13 12 11 10 9 8 7 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:04 N/A Reserved N/A N/A D03 R/W PRO 0 Enable promiscuous mode; receive all frames D02 R/W PRM 0 Accept all multicast frames D01 R/W PRA 0 Accept multicast frames using the hash table D00 R/W BROAD
..... ETHERNET COMMUNICATION MODULE Statistics registers HT2 Address: A060 0508 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 HT2 15 14 13 12 11 10 9 8 HT2 Register bit assignment Bits Access Mnemonic Reset Description D31:00 R/W HT2 0x00000000 CRC 63:32 Statistics registers ..................................................................................
ETHERNET COMMUNICATION MODULE Statistics registers Receive statistics counters address map Receive byte counter (A060 069C) Receive packet counter (A060 06A0) Address Register Transmit and receive counters R/W A060_0694 TRMAX Transmit & receive 1024 to 1518 Byte frame counter R/W A060_0698 TRMGV Transmit & receive 1519 count to 1522 Byte good VLAN frame R/W Address Register Receive counters R/W A060_069C RBYT Receive byte counter R/W A060_06A0 RPKT Receive packet counter R/W
..... ETHERNET COMMUNICATION MODULE Statistics registers D17:00 Receive FCS error counter (A060 06A4) Receive multicast packet counter (A060 06A8) Receive broadcast packet counter (A060 06AC) R/W Reset = 0x00000 RPKT Incremented for each frame received with a length of 64 to 1518 bytes, and containing a frame check sequence (FCS) error. FCS errors are not counted for VLAN frames that exceed 1518 bytes or for any frames with dribble bits.
ETHERNET COMMUNICATION MODULE Statistics registers Receive alignment error counter (A060 06BC) Receive code error counter (A060 06C4) Receive carrier sense error counter (A060 06C8) Receive undersize packet counter (A060 06CC) Receive oversize packet counter (A060 06D0) Receive fragments counter (A060 06D4) 306 Incremented for each received frame, from 64 to 1518 bytes, that contains an invalid FCS and has dribble bits (that is, is not an integral number of bytes).
..... ETHERNET COMMUNICATION MODULE Statistics registers Receive jabber counter (A060 06D8) Transmit statistics counters address map Transmit byte counter (A060 06E0) www.digiembedded.com Incremented for frames received that exceed 1518 bytes (non-VLAN) or 1522 bytes (VLAN) and contain an invalid FCS, including alignment errors. This counter does not increment when a packet is truncated to 1518 (non-VLAN) or 1522 (VLAN) bytes by MAXF.
ETHERNET COMMUNICATION MODULE Statistics registers Transmit packet counter (A060 06E4) Transmit multicast packet counter (A060 06E8) Incremented for each transmitted packet (including bad packets, excessive deferred packets, excessive collision packets, late collision packets, and all unicast, broadcast, and multicast packets). D31:18 R Reset = Read as 0 Reserved D17:00 R/W Reset = 0x00000 TPKT Incremented for each multicast valid frame transmitted (excluding broadcast frames).
..... ETHERNET COMMUNICATION MODULE Statistics registers Transmit multiple collision packet counter (A060 0700) Transmit late collision packet counter (A060 0704) Transmit excessive collision packet counter (A060 0708) Transmit total collision packet counter (A060 070C) Transmit jabber frame counter (A060 0718) Transmit FCS error counter (A060 071C) www.digiembedded.com Incremented for each frame transmitted that experienced 2–15 collisions (including any late collisions) during transmission.
ETHERNET COMMUNICATION MODULE Statistics registers Transmit oversize frame counter (A060 0724) Transmit undersize frame counter (A060 0728) Transmit fragment counter (A060 072C) General Statistics registers address map Incremented for each transmitted frame that exceeds 1518 bytes (NON_VLAN) or 1532 bytes (VLAN) and contains a valid FCS. D31:12 R Reset = Read as 0 Reserved D11:00 R/W Reset = 0x000 TOVR Incremented for every frame less than 64 bytes, with a correct FCS value.
..... ETHERNET COMMUNICATION MODULE Statistics registers Register 31 C164 Register bit assignment Carry Register 2 www.digiembedded.
ETHERNET COMMUNICATION MODULE Statistics registers Register 31 30 29 28 27 26 25 24 23 22 21 20 Reserved Register bit assignment Carry Register 1 Mask register 312 15 14 13 12 11 C2 TUN C2 TFG C2 TBY C2 TPK 10 C2TMC C2TBC 19 18 17 16 C2 JTB C2 TFC Rsvd C2 TOV 1 0 9 8 7 6 5 4 3 2 Rsvd C2TDF C2 TED C2 TSC C2 TMA C2 TLC C2 TXC C2 TNC Bits Access Mnemonic Reset Description D31:20 N/A Reserved N/A N/A D19 R/C C2TJB 0 Carry register 2 TJBR count
..... ETHERNET COMMUNICATION MODULE Statistics registers Register 31 30 M164 M1127 Register bit assignment www.digiembedded.
ETHERNET COMMUNICATION MODULE Statistics registers Carry Register 2 Mask register Address: A060 073C Register 31 30 29 28 27 26 25 24 23 22 21 20 Reserved Register bit assignment 314 19 18 17 16 M2 JTB M2 TFC Not used M2 TOV 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 M2 TUN M2 TFG M2 TBY M2 TPK M2 TMC M2TBC Not used M2TDF M2 TED M2 TSC M2 TMA M2 TLC M2 TXC M2 TNC Bits Access Mnemonic Reset Description D31:20 N/A Reserved N/A N/A D19 R/W M2TJB
..... ETHERNET COMMUNICATION MODULE RX_A Buffer Descriptor Pointer register RX_A Buffer Descriptor Pointer register ..................................................................................
ETHERNET COMMUNICATION MODULE RX_C Buffer Descriptor Pointer register RX_C Buffer Descriptor Pointer register ..................................................................................
..... ETHERNET COMMUNICATION MODULE Ethernet Interrupt Status register Ethernet Interrupt Status register .................................................................................. Address: A060 0A10 The Ethernet Interrupt Status register contains status bits for all of the Ethernet interrupt sources. Each interrupt status bit is assigned to either the RX or TX Ethernet interrupt; bits D25:16 are assigned to the RX interrupt and D06:00 are assigned to the TX interrupt.
ETHERNET COMMUNICATION MODULE Ethernet Interrupt Status register Bits Access Mnemonic Reset D21 R/C RXDONEB 0 Description Assigned to RX interrupt. Complete receive frame stored in pool B of system memory. D20 R/C RXDONEC 0 Assigned to RX interrupt. Complete receive frame stored in pool C of system memory. D19 R/C RXDONED 0 Assigned to RX interrupt. Complete receive frame stored in pool D of system memory. D18 R/C RXNOBUF 0 Assigned to RX interrupt.
..... ETHERNET COMMUNICATION MODULE Ethernet Interrupt Enable register Bits Access Mnemonic Reset D01 R/C TXERR 0 Description Last frame not transmitted successfully. Assigned to TX interrupt. See “Ethernet Interrupt Status register” on page 317 for information about restarting the transmitter when this bit is set. D00 R/C TXIDLE 0 TX_WR logic has no frame to transmit. Assigned to TX interrupt.
ETHERNET COMMUNICATION MODULE TX Buffer Descriptor Pointer register Bits Access Mnemonic Reset Description D16 R/W EN_RXBR 0 Enable the RXBR interrupt bit. D15:07 N/A Reserved N/A N/A D06 R/W EN_STOVFL 0 Enable the STOVFL interrupt bit. D05 R/W Not used 0 Always write as 0. D04 R/W EN_TXBUFC 0 Enable the TXBUFC interrupt bit. D03 R/W EN_TXBUFNR 0 Enable the TXBUFNR interrupt bit. D02 R/W EN_TXDONE 0 Enable the TXDONE interrupt bit.
..... ETHERNET COMMUNICATION MODULE Transmit Recover Buffer Descriptor Pointer register Transmit Recover Buffer Descriptor Pointer register ..................................................................................
ETHERNET COMMUNICATION MODULE TX Stall Buffer Descriptor Pointer register Register bit assignment Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07:00 R TXERBD 0x00 Contains the pointer (in the TX buffer descriptor RAM) to the last buffer descriptor of a frame that was not successfully transmitted. TXERBD is loaded by the TX_WR logic when a transmit frame is aborted by the MAC or when the MAC finds a CRC error in a frame.
..... ETHERNET COMMUNICATION MODULE RX_A Buffer Descriptor Pointer Offset register Register bit assignment Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07:00 R TXSPTR 0x00 If the TX runs out of frames to send, it sets TXIDLE in the Ethernet Interrupt Status register and stores the pointer (in the TX buffer descriptor RAM) to the buffer descriptor that did not have its F bit set in the TX Stall Buffer Descriptor Pointer register.
ETHERNET COMMUNICATION MODULE RX_B Buffer Descriptor Pointer Offset register RX_B Buffer Descriptor Pointer Offset register ..................................................................................
..... ETHERNET COMMUNICATION MODULE RX_D Buffer Descriptor Pointer Offset register Register bit assignment Bits Access Mnemonic Reset Description D31:11 N/A Reserved N/A N/A D10:00 R RXCOFF 0x000 Contains an 11-bit byte offset from the start of the pool C ring. The offset is updated at the end of the RX packet, and will have the offset to the next buffer descriptor that will be used. RXCOFF can be used to determine where the RX_RD logic will put the next packet.
ETHERNET COMMUNICATION MODULE RX Free Buffer register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 Reserved Register bit assignment TXOFF Bits Access Mnemonic Reset Description D31:10 N/A Reserved N/A N/A D09:00 R TXOFF 0x000 Contains a 10-bit byte offset from the start of the transmit ring in the TX buffer descriptor RAM.
..... ETHERNET COMMUNICATION MODULE Multicast Address Filter registers Bits Access Mnemonic Reset Description D01 W RXFREEB 0 Pool B free bit D00 W RXFREEA 0 Pool A free bit Multicast Address Filter registers .................................................................................. Each of the eight entries in the multicast address filter logic has individual registers to hold its 48-bit multicast address. The multicast address for each entry is split between two registers.
ETHERNET COMMUNICATION MODULE Multicast Address Filter registers Multicast Low Address Filter Register #6 Address: A060 0A58 Multicast Low Address Filter Register #7 Address: A060 0A5C Multicast High Address Filter Register #0 Address: A060 0A60 Multicast High Address Filter Register #1 Multicast High Address Filter Register #2 Multicast High Address Filter Register #3 Multicast High Address Filter Register #4 Multicast High Address Filter Register #5 328 D31:00 D31:00 R/W R/W Default = 0x
..... ETHERNET COMMUNICATION MODULE Multicast Address Mask registers Multicast High Address Filter Register #6 Multicast High Address Filter Register #7 Address: A060 0A78 D31:16 R Default = 0x0000 0000 Reserved (read as 0) D15:00 R/W Default = 0x0000 0000 MFILTH6 Address: A060 0A7C D31:16 R Default = 0x0000 0000 Reserved (read as 0) D15:00 R/W Default = 0x0000 0000 MFILTH7 Multicast Address Mask registers ................................................................................
ETHERNET COMMUNICATION MODULE Multicast Address Mask registers Multicast Low Address Mask Register #4 Address: A060 0A90 Multicast Low Address Mask Register #5 Address: A060 0A94 Multicast Low Address Mask Register #6 Address: A060 0A98 Multicast Low Address Mask Register #7 Address: A060 0A9C Multicast High Address Mask Register #0 Address: A060 0AA0 Multicast High Address Mask Register #1 Multicast High Address Mask Register #2 Multicast High Address Mask Register #3 Multicast High Address
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ETHERNET COMMUNICATION MODULE TX Buffer Descriptor RAM Register bit assignment Bits Access Mnemonic Reset Description D31:08 R Reserved N/A Read as 0 D07 R/W MFILTEN7 0x0000 0000 Enable entry 7 of multicast address filter 0 1 D06 R/W MFILTEN6 0x0000 0000 Enable entry 6 of multicast address filter 0 1 D05 R/W MFILTEN5 0x0000 0000 R/W MFILTEN4 0x0000 0000 R/W MFILTEN3 0x0000 0000 R/W MFILTEN2 0x0000 0000 R/W MFILTEN1 0x0000 0000 R/W MFILTEN0 0x0000 0000 Disable entry
..... ETHERNET COMMUNICATION MODULE RX FIFO RAM Offset+4 D31:11 R/W Not used D10:00 R/W Buffer length D31:00 R/W Destination address (not used) D31 R/W W Wrap D30 R/W I Interrupt on buffer completion D29 R/W L Last buffer on transmit frame D28 R/W F Buffer full D27:16 R/W Reserved N/A D15:00 R/W Status Transmit status from MAC Offset+8 Offset+C See “Transmit buffer descriptor format” on page 270, for more information about the fields in Offset+C. RX FIFO RAM .........
ETHERNET COMMUNICATION MODULE Sample hash table code Sample hash table code .................................................................................. This sample C code describes how to calculate hash table entries based on 6-byte Ethernet destination addresses and a hash table consisting of two 32-bit registers (HT1 and HT2). HT1 contains locations 31:0 of the hash table; HT2 contains locations 63:32 of the hash table.
..... ETHERNET COMMUNICATION MODULE Sample hash table code (*MERCURY_EFE).ht2.bits.data = SWAP32(hash_table[1]); (*MERCURY_EFE).ht1.bits.data = SWAP32(hash_table[0]); } / * * * Function: void eth_make_hash_table (WORD32 *hash_table) * * Description: * * This routine creates a hash table based on the CRC values of * the MAC addresses setup by set_hash_bit(). The CRC value of * each MAC address is calculated and the lower six bits are used * to generate a value between 0 and 64.
ETHERNET COMMUNICATION MODULE Sample hash table code / * * * Function: void set_hash_bit (BYTE *table, int bit) * * Description: * * This routine sets the appropriate bit in the hash table.
.....
ETHERNET COMMUNICATION MODULE Sample hash table code bp = rotate (bp, RIGHT, 1); } } // CRC calculation done.
..... EXTERNAL DMA DMA transfers External DMA C H A P T E R 6 T he external DMA interface provides two external channels for external peripheral support. Each DMA channel moves data from the source address to the destination address. These addresses can specify any peripheral on the AHB bus but, ideally, they specify an external peripheral and external memory. DMA transfers ..................................................................................
EXTERNAL DMA DMA buffer descriptor DMA buffer descriptor .................................................................................. All DMA channels use a buffer descriptor. When a DMA channel is activated, it reads the DMA buffer descriptor that the Buffer Descriptor Pointer register points to. A DMA buffer descriptor is always fetched using an AHB INCR4 transaction to maximize AHB bus bandwidth. When the current descriptor is retired, the next descriptor is accessed from a circular buffer.
..... EXTERNAL DMA Descriptor list processing Note: Optimal performance is achieved when the destination address is aligned on a word boundary. Status This field is not used. Read back 0x0000. Wrap (W) bit The Wrap (W) bit, when set, tells the DMA controller that this is the last buffer descriptor within the continuous list of descriptors. The next buffer descriptor is found using the initial DMA channel buffer descriptor pointer.
EXTERNAL DMA Peripheral DMA read access Peripheral DMA read access .................................................................................. The diagrams in this section describe how the DMA engine performs read accesses of an external peripheral. The CLK signal shown is for reference, and its frequency is equal to the speed grade of the part. The peripheral data enable signal (PDEN) is an AND function of the active states of the st_cs_n[n] and st_oe_n signals.
..... EXTERNAL DMA Peripheral DMA write access Peripheral DMA single read access CLK st_cs_n[n] st_oe_n ADDR Address Valid PDEN DQ DATA VALID Peripheral DMA burst read access CLK st_cs_n[n] st_oe_n ADDR ADDR0 ADDR1 PDEN DQ DATA0 DATA1 Peripheral DMA write access .................................................................................. The diagrams in this section describe how the DMA engine performs write accesses of an external peripheral.
EXTERNAL DMA Peripheral REQ and DONE signaling Determining the width of PDEN Use the memory controller’s Static Memory Write Delay register and Static Memory Write Enable Delay register to determine the width of the PDEN assertion. Peripheral DMA single write access CLK st_cs_n[n] we_n PDEN ADDR & DATA Addr/Data Valid Peripheral DMA burst write access CLK st_cs_n[n] we_n PDEN ADDR & DATA ADDR0/DATA0 ADDR1/DATA1 ADDR2/DATA2 Peripheral REQ and DONE signaling ................................
..... EXTERNAL DMA Static RAM chip select configuration DONE signal The external peripheral can terminate the DMA transfer at any time by asserting the DONE signal. The peripheral must also deassert the REQ signal when it asserts the DONE signal. The DONE signal can be asserted during a transfer but if the peripheral is configured for burst access, the burst completes.
EXTERNAL DMA Control and Status registers Register name Field Value Comment Output Enable Delay WOEN User-defined For most applications, this field can be set to 0. Write Enable Delay WWEN User-defined For most applications, this field can be left in the default state. Write Delay WTWR User-defined For most applications, this field can be left in the default state. Turn Delay WTTN User-defined For most applications, this field can be left in the default state.
..... EXTERNAL DMA DMA Control register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 BuffDesc 15 14 13 12 11 10 9 8 BuffDesc Register bit assignment Bit(s) Access Mnemonic Reset Description D31:00 R/W BuffDesc 0x0000_0000 32-bit pointer to a buffer descriptor DMA Control register ..................................................................................
EXTERNAL DMA DMA Control register Register bit assignment Bit(s) Access Mnemonic Reset Description D31 R/W CE 0 Channel enable Enables and disables DMA operations as required. After a DMA channel has entered the IDLE state for any reason, this field must be written to a 1 to initiate further DMA transfers. D30 R/W CA 0 Channel abort When set, causes the current DMA operation to complete and closes the buffer.
..... EXTERNAL DMA DMA Control register Bit(s) Access Mnemonic Reset Description D22:21 R/W DB 0 Destination burst Defines the AHB maximum burst size allowed when writing to the destination. Note that the destination must have enough space, as defined by this register setting, before asserting REQ.
EXTERNAL DMA DMA Status and Interrupt Enable register Bit(s) Access Mnemonic Reset Description D16 R/W RST 0 Reset Forces a reset of the DMA channel. Writing a 1 to this field forces all fields in this register, except the index field, to the reset state. The reset field is written with the value specified on signals HWDATA[9:0]. This field always reads back a 0.
..... EXTERNAL DMA DMA Status and Interrupt Enable register Register bit assignment Bit(s) Access Mnemonic Reset Description D31 R/W1C NCIP 0 Normal completion interrupt pending Set when a buffer descriptor has been closed. A normal DMA channel completion occurs when the BLEN count (D15:00) expires to zero and the L but in the buffer descriptor is set or when the peripheral device signals completion.
EXTERNAL DMA DMA Peripheral Chip Select register Bit(s) Access Mnemonic Reset Description D24 R/W NCIE 0 Enable NCIP interrupt generation. D23 R/W ECIE 0 Enable ECIE interrupt generation. This interrupt should always be enabled during normal operation. D22 R/W NRIE 0 Enable NRIP interrupt generation. D21 R/W CAIE 0 Enable CAIP interrupt generation. This interrupt should always be enabled during normal operation. D20 R/W PCIE 0 Enable PCIP interrupt generation.
..... EXTERNAL DMA DMA Peripheral Chip Select register Register bit assignment Bit(s) Access Mnemonic Reset Definition D31:02 R/W Not used 0 This field must always be set to 0. D01:00 R/W SEL 0 Chip select Defines which of the four memory interface chip select signals (nmpmcstcsout[n]) is connected to the external peripheral. 00 01 10 11 www.digiembedded.
EXTERNAL DMA DMA Peripheral Chip Select register 354 Hardware Reference NS9215
..... AES DATA ENCRYPTION/DECRYPTION MODULE AES Data Encryption/Decryption Module C H A P T E R 6 T he AES data encryption/decryption module provides IPSec-compatible network security to processor-based systems. The AES core module implements Rijndael encoding/decoding in compliance with the NIST Advanced Encryption Standard (AES). Features Processes 32 bits at a time. Is programmable for 128-, 192-, or 256-bit key lengths. Supports ECB, CBC, OFB, CTR, and CCM cipher modes.
AES DATA ENCRYPTION/DECRYPTION MODULE AES DMA buffer descriptor Block diagram From System Memory To System Memory Ch 1 Ext DMA Source Ch 1 Ext DMA Destination Mode and Control IV Key Expander FIFO Data blocks Expanded Key Data Out FIFO AES Engine Data In The AES module works on 128-bit blocks of data.
..... AES DATA ENCRYPTION/DECRYPTION MODULE AES DMA buffer descriptor AES buffer descriptor diagram 31 30 29 28 16 15 OFFSET + 0 Source address Destination buffer length OFFSET + 4 Source buffer length OFFSET + 8 OFFSET + C 0 Destination address W I L F Reserved AES Op AES control Field definitions follow. Source address [pointer] The source address pointer identifies the starting location of the source data. The source address can be aligned to any byte boundary.
AES DATA ENCRYPTION/DECRYPTION MODULE AES DMA buffer descriptor AES op code Bits Used for Values [5:4] Key size 00 01 10 [6] Additional authentication data (CCM mode only) 0 1 [9:7] L-par (CCM mode only) N/A [10] Reserved N/A [13:11] M-par (CCM mode only) N/A [15:14] Reserved N/A 128 bits 192 bits 256 bits No additional data Additional data used Indicates the contents of the data buffer associated with this descriptor: 000 Non-AES memory-to-memory or external DMA mode 001 Key buf
..... AES DATA ENCRYPTION/DECRYPTION MODULE Decryption The DMA channel does not try a transfer when the F bit is clear. The DMA channel enters an idle state upon fetching a buffer descriptor with the F bit cleared. When the F bit is modified by the device driver, the device driver must also write an ‘I’ to the CE bit (in the DMA Control register) to activate the idle channel. Decryption ..................................................................................
AES DATA ENCRYPTION/DECRYPTION MODULE CBC, CFB, OFB, and CTR processing ECB Mode Encryption / Decryption Source DMA Operations Destination DMA Operations Key Buffer Data Buffer Encrypted or Decrypted Data CBC, CFB, OFB, and CTR processing .................................................................................. CBC, CFB, OFB, and CTR modes need an initialization vector. Software must set up this buffer descriptor sequence: Key, IV, Data.
..... AES DATA ENCRYPTION/DECRYPTION MODULE CCM mode For encryption, software must set up this buffer descriptor sequence: Key, Nonce, additional data (optional), data (used to compute the authentication code), data (used to perform the actual encryption). For decryption, software must set up this buffer descriptor sequence: Key, Nonce, Data (used to perform the actual decryption), Additional data (optional), Data (used to compute the authentication code).
AES DATA ENCRYPTION/DECRYPTION MODULE CCM mode 362 Hardware Reference NS9215
I/O Hub Module C H A P T E R 9 T he I/O hub provides access to the low speed ports on the processor through one master port on the AHB bus. The low speed ports include four UART ports, one SPI port, one I2C port, 2 multi-function controlled ports, and one analog-to-digital (A/D) port. UART channel C can be configured for HDLC operation.
I/O HUB MODULE DMA controller Block diagram to SCM Interrupt Controller AMBA AHB Bus AHB Master AHB Slave DMA Controller Rsvd Rsvd UART A UART B UART C UART D A/D SPI I2C GPIO AHB slave interface The CPU has access to the control and status registers in the DMA controller, the peripheral devices, and the GPIO configuration. DMA controller ..................................................................................
..... I/O HUB MODULE DMA controller Buffer descriptors The peripheral buffer data is held in buffers in external memory, linked together using buffer descriptors. The buffer descriptors are 16 bytes in length and are located contiguously in external memory.
I/O HUB MODULE DMA controller For transmit channels. CPU sets the F bit after the data is written to a buffer. The DMA controller clears this bit as each buffer is read from external memory. If the DMA controller ever finds that this bit is not set when the buffer descriptor is read, the NRIP bit is set in the Interrupt Status register and the DMA controller stops immediately and goes to the ERROR state. The CPU must clear the CE bit to restore the DMA.
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I/O HUB MODULE Control and status register address maps 2 Verifies that the data buffer is valid by making sure the F bit is set to 1. 3 Reads the first data buffer, in 16-byte bursts. 4 Continues to process the buffer descriptors and data buffers until all data has been transmitted from the buffer descriptor with the L bit set to 1. The DMA controller interrupts the CPU if the I bit is set to a 1. 5 Remains in the IDLE state until the channel enable bit is set to a 0, then set to a 1 again.
..... I/O HUB MODULE Control and status register address maps Note: UART A register address map UART B register address map www.digiembedded.com Registers 9000_0000 – 9000_7FFF and registers 9000_8000 – 9000_FFFF are reserved.
I/O HUB MODULE Control and status register address maps UART C register address map UART D register address map 370 Register Offset Description (31:00) 0x9001_8030 – 0x9001_8FFF Reserved 0x9001_9000 – 0x9001_9FFF UART B CSR Space Register Offset Description (31:00) 0x9002_0000 UART C Interrupt and FIFO Status 0x9002_0004 UART C DMA RX Control 0x9002_0008 UART C DMA RX Buffer Descriptor Pointer 0x9002_000C UART C DMA RX Interrupt Configuration register 0x9002_0010 UART C Direct Mode RX
..... I/O HUB MODULE Control and status register address maps SPI register address map AD register address map Reserved I 2C register address map Reserved www.digiembedded.
I/O HUB MODULE [Module] Interrupt and FIFO Status register RTC register address map IO Hardware Assist register address map (0) IO Hardware Assist register address map (1) IO register address map (0) IO register address map (1) Register Offset Description (31:00) 0x9006_0000 – 0x9006_00BF RTC CSR Space 0x9006_0000 – 0x9006_00FC 64-byte Battery Backed RAM Register Offset Description (31:00) 0x9006_8000 – 0x9006_FFFF IO Hardware Assist CSR Space for Flexible I/O Module 0 Register Offset Desc
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I/O HUB MODULE [Module] Interrupt and FIFO Status register Bit(s) Access Mnemonic Reset Description D26 R/W* RXFOFIP 0x0 RX FIFO overflow interrupt pending Set when the RX FIFO finds an overflow condition. D25 R/W* RXFSRIP 0x0 RX FIFO service request interrupt pending (RX) Set when the RX FIFO level rises above the receive FIFO threshold (in the RX Interrupt Configuration register).
..... I/O HUB MODULE [Module] DMA RX Control Bit(s) Access Mnemonic Reset Description D18 R MODIP 0x0 Module interrupt pending The hardware module has asserted an interrupt. Software must read the appropriate Interrupt Status register to determine the cause. D17:16 N/A Reserved N/A N/A D15 R RXPBUSY 0x0 0 1 Peripheral idle Peripheral busy Note: Applicable only for channels connected to the flexible I/O module processors.
I/O HUB MODULE [Module] DMA RX Buffer Descriptor Pointer Register 31 30 29 28 CE CA FLEX I/O DIRECT 15 14 13 12 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 11 10 9 8 7 INDEX STATE Register bit assignment Bit(s) Access Mnemonic Reset Description D31 R/W CE 0x0 Channel enable 0 1 D30 R/W CA 0x0 Disable DMA operation Enable DMA operation Channel abort When set, causes the current DMA operation to complete and closes the buffer.
..... I/O HUB MODULE [Module] RX Interrupt Configuration register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RXBDP 15 14 13 12 11 10 9 8 7 RXBDP Register bit assignment Bit(s) Access Mnemonic Reset Description D31:00 R/W RXBDP 0x0 The first buffer descriptor in the ring. Used when the W bit is found, which indicates the last buffer descriptor in the list. [Module] RX Interrupt Configuration register ................................
I/O HUB MODULE [Module] Direct Mode RX Status FIFO Bit(s) Access Mnemonic Reset Description D26 R/W RXFOFIE 0x0 Enable the RXFOFIP interrupt. D25 R/W RXFSRIE 0x0 Enable the RXFSRIP interrupt. D24 R/W RXNCIE 0x0 Enable the RXNCIP interrupt. D23 R/W RXECIE 0x0 Enable the RXECIP interrupt. D22 R/W RXNRIE 0x0 Enable the RXNRIP interrupt. D21 R/W RXCAIE 0x0 Enable the RXCAIP interrupt. D20 R/W RXPCIE 0x0 Enable the RXPCIP interrupt.
..... I/O HUB MODULE [Module] Direct Mode RX Data FIFO Register bit assignment Bit(s) Access Mnemonic Reset Description D31:12 N/A Reserved N/A N/A D11:09 R BYTE N/A Number of bytes in the current 32-bit location. D08 N/A Reserved N/A N/A D07 R FFLAG N/A Full flag Indicates that the FIFO went full when the current location was written. D06:00 R PSTAT N/A General peripheral status, unique to the peripheral attached to the channel. [Module] Direct Mode RX Data FIFO .........
I/O HUB MODULE [Module] DMA TX Control [Module] DMA TX Control .................................................................................. Addresses: 9000_0018 / 9000_8018 / 9001_0018 / 9001_8018 / 9002_0018 / 9002_8018 / 9003_0018 The DMA TX Control register contains control register settings for each transmit DMA channel.
..... I/O HUB MODULE [Module] DMA TX Buffer Descriptor Pointer [Module] DMA TX Buffer Descriptor Pointer .................................................................................. Addresses: 9000_001C / 9000_801C / 9001_001C / 9001_801C / 9002_001C / 9002_801C / 9003_001C The DMA TX Buffer Descriptor Pointer is the address of the first buffer descriptor for each DMA channel.
I/O HUB MODULE [Module] Direct Mode TX Data FIFO Register bit assignment Bit(s) Access Mnemonic Reset Description D31:28 R/W TXTHRS 0xF TX FIFO threshold An interrupt is generated when the FIFO level drops below this level. D27 N/A Reserved N/A N/A D26 R/W TXFUFIE 0x0 Enable the TXFUFIP interrupt. D25 R/W TXFSRIE 0x0 Enable the TXFSRIP interrupt. D24 R/W TXNCIE 0x0 Enable the NCIP interrupt. D23 R/W TXECIE 0x0 Enable the ECIP interrupt.
..... I/O HUB MODULE [Module] Direct Mode TX Data Last FIFO Register bit assignment Bit(s) Access Mnemonic Reset Description D31:00 W TXD 0x0 TX Data FIFO Write register [Module] Direct Mode TX Data Last FIFO ..................................................................................
I/O HUB MODULE [Module] Direct Mode TX Data Last FIFO 384 Hardware Reference NS9215 31 March 2008
..... S E R I A L C O N T RO L M O D U L E : U A RT Serial Control Module: UART C H A P T E R 1 0 T he processor ASIC supports four independent universal asynchronous receiver/transmitter (UART) channels (A through D). Each channel supports several modes, conditions, and formats. Features DMA transfers to and from system memory Independent receive and transmit programmable bit-rate generators High speed data transfer up to 1.
S E R I A L C O N T RO L M O D U L E : U A RT Normal mode operation UART module structure UART RI CTS DCD DSR DTR RTS RXD TXD AHB Bus ref_clk int data[31:0] be[1:0] status[6:0] write Receive FIFO Interface read be[1:0] data[31:0] valid Transmit FIFO Interface IO Hub Normal mode operation .................................................................................. The UART achieves normal mode operation by programming the UART and Wrapper configuration registers.
..... S E R I A L C O N T RO L M O D U L E : U A RT Baud rate generator Control register Field Value Comment UART Interrupt Enable register (0x104) ETBEI 0x1 Enable the Transmitter Holding Register Empty Interrupt. enables the Wrapper to write a transmit character to the UART. Wrapper Configuration register TX FLOW Software 1 TX Enabled RXEN 1 Enable Wrapper receive function TXEN 1 Enable Wrapper transmit function Baud rate generator ....................................................
S E R I A L C O N T RO L M O D U L E : U A RT Hardware-based flow control Hardware-based flow control .................................................................................. The UART module provides expanded functionality for hardware-based flow control. The RTS signal normally indicates the state of the receive FIFO. The CTS signal normally halts the transmitter. With this UART module, the RI, CTS, DCD, or DSR signals can halt the transmitter.
..... S E R I A L C O N T RO L M O D U L E : U A RT ARM wakeup on character recognition character completes, regardless of any flow control mechanism that might stall normal data transmission. Use the Force Transmit Character Control register to program this operation. Force character transmission procedure Collecting feedback These steps outline a single force character transmission operation: 1 Read the Force Transmit Character Control register and verify that the ENABLE field is 0.
S E R I A L C O N T RO L M O D U L E : U A RT Wrapper Control and Status registers Wrapper Control and Status registers .................................................................................. The configuration registers for UART module A start at 0x9001_1000, UART module B start at 0x9001_9000, UART module C start at 0x9002_1000, and UART module D start at 9002_9000. Register address map These are the configuration registers for UART module A.
..... S E R I A L C O N T RO L M O D U L E : U A RT Wrapper Configuration register Address Register 9001_1114 UART Line Status 9001_1118 UART Modem Status 9001_111C UART Scratch Wrapper Configuration register .................................................................................. Address: 9001_1000 / 9001_9000 / 9002_1000 / 9002_9000 This is the primary Wrapper Configuration register.
S E R I A L C O N T RO L M O D U L E : U A RT Wrapper Configuration register Bits Access Mnemonic Reset D17 R/W RXFLUSH 0 Description Resets the contents of the 64-byte RXFIFO. Write a 1, then a 0 to reset the FIFO. D16 R/W TXFLUSH N/A Resets the contents of the 64-byte TX FIFO. Write a 1, then a 0 to reset the FIFO. D15:14 R RXBYTES 00 Indicates how many bytes are pending in the wrapper.
..... S E R I A L C O N T RO L M O D U L E : U A RT Interrupt Enable register Bits Access Mnemonic Reset Description D03:02 R/W RS485OFF 00 RS485 transceiver deassertion control In bit times after the stop bit period 00 01 10 11 D01:00 R/W RS485ON 00 0 1 1.5 2 RS485 transceiver assertion control In bit times before the falling edge of the start bit 00 01 10 11 0 1 1.5 2 Interrupt Enable register ..................................................................................
S E R I A L C O N T RO L M O D U L E : U A RT Interrupt Enable register Bits Access Mnemonic Reset Description D19 R/W OFLOW 0 Enable overflow error Enables interrupt generation if the 4-character FIFO in the UART overflows. Note: D18 R/W PARITY 0 This should not happen in a properly configured system. Enable parity error Enables interrupt generation when a character is received with a parity error.
..... S E R I A L C O N T RO L M O D U L E : U A RT Interrupt Status register Bits Access Mnemonic Reset Description D06 R/W DCD 0 Enable data carrier Enables interrupt generation whenever a stat change occurs on input signal DCD. D05 R/W CTS 0 Enable clear to send Enables interrupt generation whenever a state change occurs on input signal CTS. D04 R/W RI 0 Enable ring indicator Enables interrupt generation whenever a state change occurs on input signal RI.
S E R I A L C O N T RO L M O D U L E : U A RT Interrupt Status register Register 31 30 29 28 27 26 25 24 23 22 14 13 BGAP RXCLS CGAP Register bit assignment 12 11 10 20 19 18 Reser FORCE OFLOW PARITY ved Not used 15 21 9 8 7 MATCH MATCH MATCH MATCH MATCH DSR 4 3 2 1 0 6 5 4 3 2 DCD CTS RI TBC RBC Bits Access Mnemonic Reset Description D31:22 R/W Not used 0 Write this field to 0.
..... S E R I A L C O N T RO L M O D U L E : U A RT Interrupt Status register Bits Access Mnemonic Reset Description D11 R/W1TC MATCH3 0 Character match3 Indicates that a receive character match has occurred against the Receive Match Register 3. D10 R/W1TC MATCH2 0 Character match2 Indicates that a receive character match has occurred against the Receive Match Register 2.
S E R I A L C O N T RO L M O D U L E : U A RT Receive Character GAP Control register Bits Access Mnemonic Reset Description D01 R/W1TC TX_IDLE 0 Transmit idle Indicates that the transmitter has moved from the active state to the idle state. The transmitter moves from the active state to the idle state when the transmit FIFO is empty and the transmitter is not actively shifting out data.
..... S E R I A L C O N T RO L M O D U L E : U A RT Receive Buffer GAP Control register Receive Buffer GAP Control register .................................................................................. Address: 9001_1010 / 9001_9010 / 9002_1010 / 9002_9010 The Receive Buffer GAP Control register configures the receive buffer gap control logic. The buffer gap timer starts when the first character in a new buffer is received.
S E R I A L C O N T RO L M O D U L E : U A RT Receive Character-Based Flow Control register The Receive Character Match Control registers configure the receive character match control logic. Each UART module has five Receive Character Match Control registers.
..... S E R I A L C O N T RO L M O D U L E : U A RT Receive Character-Based Flow Control register Caution:Be aware that if multiple matches occur, an XOFF assertion will supersede an XON assertion. Register 31 30 29 EN ABLE 15 28 27 26 25 24 23 22 Not used 14 13 12 21 11 10 9 8 7 6 5 Access Mnemonic Reset Description D31:11 R Not used 0 Write this field to 0.
S E R I A L C O N T RO L M O D U L E : U A RT Force Transmit Character Control register Bits Access Mnemonic Reset Description D05:04 R/W FLOW2 0 Flow control enable Allows you to define flow characteristics using the DATA and MASK fields on the Receive Character Match Control Register 2. Note: The ENABLE field has no effect on the flow control logic.
..... S E R I A L C O N T RO L M O D U L E : U A RT ARM Wakeup Control register Register 31 30 29 28 27 26 25 EN BUSY ABLE 15 14 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Not used 13 12 11 10 9 8 Not used Register bit assignment CHAR Bits Access Mnemonic Reset Description D31 R/W ENABLE 0 Force transmit enable Use this field to force the transmitter to send the character specified in the CHAR field (D07:00).
S E R I A L C O N T RO L M O D U L E : U A RT Transmit Byte Count Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Not used 15 14 13 12 11 10 9 8 EN ABLE Not used Register bit assignment Bits Access Mnemonic Reset Description D31:01 R Not used 0 Write this field to 0. D00 R/W ENABLE 0 Enable Write a 1 to this field to enable ARM wakeup control logic. Transmit Byte Count .............................................................
..... S E R I A L C O N T RO L M O D U L E : U A RT UART Receive Buffer UART Receive Buffer .................................................................................. Address: 9001_1100 / 9001_9100 / 9002_1100 / 9002_9100, DLAB = 0, Read UART Receive Buffer is used for diagnostic purposes only.
S E R I A L C O N T RO L M O D U L E : U A RT UART Baud Rate Divisor LSB Register bit assignment Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07:00 W TBUFF 0 Transmitter data bits UART Baud Rate Divisor LSB .................................................................................. Address: 9001_1100 / 9001_9100 / 9002_1100 / 9002_9100, DLAB = 1 UART Baud Rate Divisor sets bits 07:00 of the baud rate generator divisor.
..... S E R I A L C O N T RO L M O D U L E : U A RT UART Interrupt Enable register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 Reserved Register bit assignment BRDM Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07:00 R/W BRDM 0 Bits 15:08 of the baud rate generator divisor UART Interrupt Enable register ......................................................................
S E R I A L C O N T RO L M O D U L E : U A RT UART Interrupt Identification register Bits Access Mnemonic Reset Description D02 R/W ELSI 0 Enables receive line status interrupt 0 1 D01 R/W ETBEI 0 Enables transmit holding register empty interrupt 0 1 D00 R/W ERBFI Disabled Enabled 0 Disabled Enabled Enables receive data available interrupt 0 1 Disabled Enabled UART Interrupt Identification register ..................................................................................
..... S E R I A L C O N T RO L M O D U L E : U A RT UART FIFO Control register UART FIFO Control register .................................................................................. Address: 9001_1108 / 9001_9108 / 9002_1108 / 9002_9108, Write The UART FIFO Control register controls the RX and TX 4-byte FIFOs. Note that only the FIFOEN bit (bit 01) should be set; all other bits are for diagnostic purposes only.
S E R I A L C O N T RO L M O D U L E : U A RT UART Line Control register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 DLAB SB SP EPS PEN STB Reserved 15 14 13 12 11 10 9 8 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07 R/W DLAB 0 Divisor latch access bit 0 1 D06 R/W SB 0 R/W SP 0 R/W EPS 0 R/W PEN 0 R/W STB 0 R/W WLS 0 Hardware Reference NS9215 1
..... S E R I A L C O N T RO L M O D U L E : U A RT UART Modem Control register UART Modem Control register .................................................................................. Address: 9001_1110 / 9001_9110 / 9002_1110 / 9002_9110 The UART Modem Control register controls the modem signals.
S E R I A L C O N T RO L M O D U L E : U A RT UART Modem Status register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 THRE BI FE PE OE DR Reserved 15 14 13 12 11 10 9 Reserved Register bit assignment 8 FIER TEMT Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07 R FIER N/A RX FIFO error Indicates at least one parity, framing, or break error in the RX FIFO.
..... S E R I A L C O N T RO L M O D U L E : U A RT UART Modem Status register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 DSR CTS DDCD TERI Reserved 15 14 13 12 11 10 9 Reserved Register bit assignment 8 DCD RI DDSR DCTS Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07 R DCD N/A Reflects the status of the data carrier detect input. D06 R RI N/A Reflects the status of the ring indicator.
S E R I A L C O N T RO L M O D U L E : U A RT UART Modem Status register 414 Hardware Reference NS9215
..... SERIAL CONTROL MODULE: HDLC Receive and transmit operations Serial Control Module: HDLC C H A P T E R 1 1 T he HDLC module allows full-duplex synchronous communication. Both the receiver and transmitter can select either an internal or external clock. The HDLC module encapsulates data within opening and closing flags, and sixteen bits of CRC precedes the closing flag.
SERIAL CONTROL MODULE: HDLC Clocking Receive operation In the receiver, each byte is marked with status to indicate end-of-frame, short frame, and CRC error. The receiver automatically synchronizes on flag bytes, and presets the CRC checker accordingly. If the current receive frame is not needed (for example, because it is addressed to a different station), a flag search command is available. The flag search command forces the receiver to ignore the incoming data stream until another flag is received.
..... SERIAL CONTROL MODULE: HDLC Data encoding between the opening and closing flags, except for the inserted zeroes, to the receiver data buffer. Last byte bit pattern table Last byte bit pattern Valid data bbbbbbb0 7 bbbbbb01 6 bbbbb011 5 bbbb0111 4 bbb01111 3 bb011111 2 b0111111 1 Data encoding ..................................................................................
SERIAL CONTROL MODULE: HDLC Digital phase-locked-loop (DPLL) operation: Encoding HDLC Clock NRZ Data NRZI NRZI Biphase-Level Biphase-Space Biphase-Space Biphase-Mark Biphase-Mark data 1 0 1 1 0 0 1 0 Digital phase-locked-loop (DPLL) operation: Encoding .................................................................................. In the HDLC module, the internal clock comes from the output of the dedicated divider.
..... SERIAL CONTROL MODULE: HDLC DPLL operation: Adjustment ranges and output clocks DPLL-tracked bit cell boundaries The DPLL counter normally counts by 16 but if a transition occurs earlier or later than expected, the count is modified during the next count cycle. If the transition occurs earlier than expected, the bit cell boundaries are early with respect to the DPLL-tracked cell boundaries and the count is shortened by either one or two counts.
SERIAL CONTROL MODULE: HDLC DPLL operation: Adjustment ranges and output clocks Bit cell NRZI adj none add one add two subtract two subtract one none NRZI Clock Bi-L adj ignore transitions subtract one none add one ignore transitions Bi-L Clock Bi-S adj none add one ignore transitions subtract one none none add one ignore transitions subtract one none Bi-S Clock Bi-M adj Bi-M Clock NRZ and NRZI encoding With NRZ and NRZI encoding, all transitions occur on bit-cell boundaries
..... SERIAL CONTROL MODULE: HDLC Normal mode operation only uses the clock transitions to track the bit-cell boundaries, by ignoring all transitions occurring outside a window around the center of the bit-cell. The window is half a bit-cell wide. Because the clock transitions are guaranteed, the DPLL requires that they always be present. If no transition is found in the window around the center of the bit-cell for two successive bit-cells, the DPLL is not in lock and immediately enters search mode.
SERIAL CONTROL MODULE: HDLC Wrapper and HDLC Control and Status registers Control register Field Value Comment Wrapper Configuration register RXEN 1 Enable Wrapper receive function TXEN 1 Enable Wrapper transmit function Wrapper and HDLC Control and Status registers .................................................................................. The configuration registers for the HDLC module are located at 0x9002_9000.
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SERIAL CONTROL MODULE: HDLC Interrupt Enable register Bits Access Mnemonic Reset Description D04 R/W LL 0 Local loopback Provides an internal local loopback feature. When the LL field is set to 1, the transmit HDLC data signal is connected to the receive HDLC data signal. D03:00 N/A Reserved N/A N/A Interrupt Enable register ..................................................................................
..... SERIAL CONTROL MODULE: HDLC Interrupt Status register Bits Access Mnemonic Reset Description D16 R/W RABORT 0 Enable receive abort error Enables interrupt generation when a frame is received with an abort. D15 N/A Reserved N/A N/A D14 R/W RXCLS 0 Software receive close Enables interrupt generation when software forces a buffer close.
SERIAL CONTROL MODULE: HDLC Interrupt Status register Register 31 30 29 28 27 26 25 24 23 22 HINT Not used 15 14 13 12 11 10 Reserv RXCLS ed Register bit assignment 21 9 8 7 6 5 Reserved 20 19 18 17 16 Reserv OFLOW ICRC VCRC RABORT ed 4 3 2 1 0 TBC RBC TX_IDLERX_IDLE Bits Access Mnemonic Reset Description D31:22 R/W Not used 0 Write this field to 0. D21 R/W1TC HINT 0 HDLC interrupt Indicates that the HDLC has generated an interrupt.
..... SERIAL CONTROL MODULE: HDLC HDLC Data Register 1 Bits Access Mnemonic Reset Description D01 R/W1TC TX_IDLE 0 Transmit idle Indicates that the transmitter has moved from the active state to the idle state. The transmitter moves from the active state to the idle state when the transmit FIFO is empty and the transmitter is not actively shifting out data. D00 R/W1TC RX_IDLE 0 Receive idle Indicates that the receiver has moved from the active state to the idle state.
SERIAL CONTROL MODULE: HDLC HDLC Data register 3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 Reserved Register bit assignment HDATA Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07:00 R/W HDATA 0 Read Write Returns the contents of the receive buffer Used for the last data byte in a frame, after which the CRC and closing flag are transmitted HDLC Data register 3 ...........
..... SERIAL CONTROL MODULE: HDLC HDLC Control Register 1 HDLC Control Register 1 .................................................................................. Address: 9002_9110 HDLC Control Register 1 configures the HDLC transmitter and receiver.
SERIAL CONTROL MODULE: HDLC HDLC Clock Divider Low Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 Reserved Register bit assignment CMODE Bits Access Mnemonic Reset Description D31:08 R Not used 0 Write this field to 0.
..... SERIAL CONTROL MODULE: HDLC HDLC Clock Divider High Use the HDLC CLock Divider Low register to set bits 07:00 of the clock divider. This is the equation for the HDLC clock rate: 29.4912 MHz HDLC rate (bps) = 16 x (DIV = 1) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 9 8 7 6 5 4 3 2 1 0 Not used 15 14 13 12 11 10 Not used Register bit assignment DIVL Bits Access Mnemonic Reset Description D31:08 R Not used 0 Write this field to 0.
SERIAL CONTROL MODULE: HDLC HDLC Clock Divider High Register bit assignment Bits Access Mnemonic Reset Description D31:08 R Not used 0 Write this field to 0. D07 R/W EN 0 Clock enable Must be set when the internal clock is used. D06:00 432 Hardware Reference NS9215 R/W DIVH 0 Seven MSBs of the divider that generates the HDLC transmit and receive clock.
..... SERIAL CONTROL MODULE: SPI Serial Control Module: SPI C H A P T E R 1 2 T he processor ASIC contains a single high speed, four-wire, serial peripheral interface (SPI) module. Features DMA transfers to and from system memory Four-wire interface (RXD, TXD, CLK, CS) Multi-drop supported through GPIO programming Master or slave operation High speed data transfer – Master: 33.33 Mbps – Slave: 7.
SERIAL CONTROL MODULE: SPI SPI controller spi_clk_in spi_rx_d spi_cs_in_n spi_cs_in_n spi_cs_out_n spi_clk_out spi_tx_d SPI module structure spi_tx_d Transmit State Machine spi_cs_out_n spi_clk data[31:0] status[6:0] be[1:0] Receive Fifo Interface write read be[1:0] data[31:0] Transmit Fifo Interface Config spi_irq AHB Bus Clock Generation valid sys_pll_out Receive State Machine spi_clk_out SPI controller .......................................................................
..... SERIAL CONTROL MODULE: SPI SPI clocking modes SPI clocking modes .................................................................................. There are four SPI clocking modes. Each mode’s characteristics are defined by the idle value of the clock, which clock edge captures data, and which clock edge drives data. The MODE field in the SPI Configuration register specifies the timing mode.
SERIAL CONTROL MODULE: SPI SPI clock generation SPI clock generation .................................................................................. The reference clock for the SPI module is the system PLL output. This clock is a nominal 300 MHz. In SPI master mode, the clock is divided down to produce the required data rate. In SPI slave mode, the divided down clock recovers the input SPI clock.
..... SERIAL CONTROL MODULE: SPI System boot-over-SPI operation Available strapping options boot_mode[1:0] Address width 00 Disabled 01 8-bit address 10 16-bit address 11 24-bit address EEPROM/FLASH header The boot-over-SPI hardware requires several pieces of user-supplied information to complete the boot operation. This information must be located in a 128-byte header starting at address zero in the external memory device. Each entry in the header is four bytes long.
SERIAL CONTROL MODULE: SPI System boot-over-SPI operation Entry Name 0x14 DynamicRefresh Description See the Memory Controller chapter. For example, the value of this entry is 0x00000025 given a 74.9 MHz AHB clock and a 7.8125μs refresh period. Ox18 DynamicReadConfig See the Memory Controller chapter.
..... SERIAL CONTROL MODULE: SPI SPI Control and Status registers SPI Control and Status registers .................................................................................. The configuration registers for the SPI module are located at 0x9003_1000. Register address map Address Register 9003_1000 SPI Configuration register 9003_1010 Clock Generation register 9003_1020 Interrupt Enable register 9003_1024 Interrupt Status register SPI Configuration register ............................
SERIAL CONTROL MODULE: SPI Clock Generation register Bits Access Mnemonic Reset Description D11:08 R/W DISCARD 0 Discard bytes Defines the number of bytes the receiver should drop when the transmitter has initiated a new operation. A new operation is defined by the chip select signal being asserted low. The programmed value defines the number of bytes to discard. The maximum number of receive bytes that can be discarded is 14. D07:06 R/W Not used 0 Write this field to 0.
..... SERIAL CONTROL MODULE: SPI Interrupt Enable register Use this register to define the data rate of the interface. This register must be programmed in three steps. Failure to follow these steps can result in unpredictable behavior of the SPI module. Register programming steps 1 Set the ENABLE field to 0. The DIVISOR field must not be changed. 2 Set the DIVISOR field to the value you want. 3 Set the ENABLE field to 1. The DIVISOR field must not be changed.
SERIAL CONTROL MODULE: SPI Interrupt Status register Use the Interrupt Enable register to enable interrupt generation on specific events. Enable the interrupt by writing a 1 to the appropriate bit field(s). Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Not used 15 14 13 12 11 10 9 8 7 Not used Register bit assignment TX_ IDLE RX_IDLE T Bits Access Mnemonic Reset Description D31:02 R/W Not used 0 Write this field to 0.
..... SERIAL CONTROL MODULE: SPI SPI timing characteristics Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Not used 15 14 13 12 11 10 9 8 7 Not used Register bit assignment TX_ IDLE RX_IDLE Bits Access Mnemonic Reset Description D31:02 R/W Not used 0 Write this field to 0. D01 R/W1TC TX_IDLE 0 Transmit idle Indicates that the transmitter has moved from the active state to the idle state.
SERIAL CONTROL MODULE: SPI SPI timing characteristics Notes: 1 The unit clock refers to the SPI master clock. 2 The SPI master interface clock duty cycle is always at least 52/48. The numbers shown here are for a 40 Mhz clock rate. 3 The numbers shown here are for a 40 Mhz clock rate. Usually, this parameter is one half the SPI master interface clock period less 1.5ns. 4 This parameter does not depend on the SPI master interface clock rate.
..... SERIAL CONTROL MODULE: SPI SPI timing characteristics 2 The numbers shown here are for a 7.5 Mhz SPI slave interface clock rate. 3 The numbers shown here are for a 300 Mhz PLL output frequency. This value must be proportionally increased with a PLL output frequency decrease. 4 This parameter does not depend on any clock frequency. SPI slave timing diagram CS# Mode3 CLK S11 S12 S13 S18 S19 Mode0 S14 S15 SDI S16 S17 SDO www.digiembedded.
SERIAL CONTROL MODULE: SPI SPI timing characteristics 446 Hardware Reference NS9215
..... I2C MASTER/SLAVE INTERFACE Physical I2C bus I2C Master/Slave Interface C H A P T E R 1 3 T he I2C master/slave interface provides an interface between the ARM CPU and the I2C bus. The I2C master/slave interface basically is a parallel-to-serial and serial-to-parallel converter. The parallel data received from the ARM CPU has to be converted to an appropriate serial form to be transmitted to an external component using the I2C bus.
I2C MASTER/SLAVE INTERFACE I2C external addresses serial clock. Serial clock modulation can be controlled by both the transmitter and receiver, based in their hosts’ service speed. Multi-master bus The I2C is a true multi-master bus with collision detection and arbitration to prevent data corruption when two or more masters initiate transfer simultaneously. If a master loses arbitration during the addressing stage, it is possible that the winning master is trying to address the transfer.
..... I2C MASTER/SLAVE INTERFACE I2C command interface I2C command interface .................................................................................. The I2C module converts parallel (8-bit) data to serial data and serial data to parallel data between the processor and the I2C bus, using a set of interface registers. Locked interrupt driven mode • The primary interface register for transmitting data is the CMD_TX_DATA_REG (write-only).
I2C MASTER/SLAVE INTERFACE I2C registers bus owner, the transaction goes through. If the module loses bus arbitration, an M_ARBIT_LOST interrupt is generated to the host processor and the command must be reissued. I2C registers .................................................................................. All registers have 8-bit definitions, but must be accessed in pairs. For example, TX_DATA_REG and CMD_REG are written simultaneously and RX_DATA_REG and STATUS_REG are read simultaneously.
..... I2C MASTER/SLAVE INTERFACE Status Receive Data register Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15 W PIPE 0x0 Pipeline mode Must be set to 0. D14 W DLEN I2C DLEN port (iic_dlen) 0x0 Must be set to 0. D13 W TXVAL 0x0 Provide new transmit data in CMD_TX_DATA_REG (tx_data_val).
I2C MASTER/SLAVE INTERFACE Master Address register Bits Access Mnemonic Reset D13 R SCMDL N/A Description Slave command lock The Slave Command register is locked. D12 R MCMDL N/A Master command lock The Master Command register is locked. D11:08 R IRQCD N/A Interrupt codes (irq_code) The interrupt is cleared if this register is read. See “Interrupt Codes” on page 455 for more information.
..... I2C MASTER/SLAVE INTERFACE Slave Address register Register bit assignment Bits Access Mnemonic Reset Description D10:01 R/W MDA 0x0 Master device address Used for selecting a slave. Represents bits 6:0 of the device address if using 7-bit address. D10:08 are not used. Represents bits 9:0 of device address if using 10-bit address. D00 R/W MAM 0x0 Master addressing mode 07 bit address mode 110 bit address mode Slave Address register ...................................................
I2C MASTER/SLAVE INTERFACE Configuration register Configuration register .................................................................................. Address: 9005 000C The Configuration register controls the timing on the I2C bus. This register also controls the external interrupt indication, which can be disabled. The I2C bus clock timing is programmable by the scl_ref value (D08:00).
..... I2C MASTER/SLAVE INTERFACE Interrupt Codes Bits Access Mnemonic Reset D12:09 R/W SFW 0xF Description Spike filter width A default value of 1 is recommended. Available values are 0–15. D08:00 R/W CLREF 0x0 clk_ref[9:1] The I2C clock on port iic_scl_out is generated by the system clock divided by the 10-bit value of clk_ref. The LSB of clk_ref cannot be programmed, and is set to 0 internally. The programmed value of clk_ref[9:1] must be greater than 3. Interrupt Codes .................
I2C MASTER/SLAVE INTERFACE Software driver Code Name Master/slave Description 0xB S_TX_DATA_1ST Slave TX data required in register TX_DATA, first byte of transaction 0xC S_RX_DATA_1ST Slave RX data available in register RX_DATA, first byte of transaction 0XD S_TX_DATA Slave TX data required in register TX_DATA 0xE S_RX_DATA Slave RX data available in register RX_DATA 0XF S_GCA Slave General call address Software driver ..............................................................
..... I2C MASTER/SLAVE INTERFACE Flow charts Flow charts ..................................................................................
I2C MASTER/SLAVE INTERFACE Flow charts Slave module (normal mode, 16bit) wait irq read rx/status S_TX_DATA_1ST irq S_RX_DATA_1ST irq write cmd S_NOP write TX_DATA_REG wait irq read rx/status S_RX_ABORT irq 1 wait irq read status S_RX_DATA irq write cmd S_NOP S_NO_ACK irq write cmd S_STOP Note: STATUS_REG and RX_DATA_REG are read simultaneously.
Real Time Clock Module C H A P T E R 1 4 T he Real Time Clock (RTC) module tracks the time of the day to an accuracy of 10 milliseconds and provides calendar functionality that tracks day, month, and year. RTC functionality RTC monitors these time periods: Year from 1900-2999 Month from 1-12 Date from 1-28, 29, 30, or 31, as a function of year and month Day of week from 1-7 Hour from 0-23, or from 1-12 with the AM/PM flag set Minute from 0-59 Second from 0.00-59.
REAL TIME CLOCK MODULE RTC configuration and status registers RTC configuration and status registers .................................................................................. All configuration registers must be accessed as 32-bit words and as single accesses only. Bursting is not allowed.
..... REAL TIME CLOCK MODULE 12/24 Hour register Register bit assignment Bits Access Mnemonic Reset Description D31:02 N/A Reserved N/A N/A D01 R/W Cal 0x1 Calendar operation 0 1 D00 R/W Time 0x1 Calendar operation enabled Calendar operation disabled Time (date, hour, minute, second) operation 0 1 Time operation enabled Time operation disabled 12/24 Hour register ..................................................................................
REAL TIME CLOCK MODULE Time register Time register .................................................................................. Address: 9006 0008 The TIme register sets the time values to the correct values, and reads the time registers. BCD is binary coded decimal.
..... REAL TIME CLOCK MODULE Calendar register Calendar register .................................................................................. Address: 9006 000C The Calendar register sets the calendar values to the correct values, and reads the calendar registers. BCD is binary coded decimal. Register 31 30 29 14 13 Reserved Register bit assignment www.digiembedded.
REAL TIME CLOCK MODULE Time Alarm register Time Alarm register .................................................................................. Address: 9006 0010 The Time Alarm register sets the time alarm. BCD is binary coded decimal.
..... REAL TIME CLOCK MODULE Calendar Alarm register Calendar Alarm register .................................................................................. Address: 9006 0014 The Calendar Alarm register sets the calendar alarm. This register programs a specific date and month when an alarm should cause an event. You cannot set an alarm that is more than one year in the future. BCD is binary coded decimal.
REAL TIME CLOCK MODULE Event Flags register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Mnth Date Hour Min Sec Hsec Reserved 15 14 13 12 11 10 9 8 7 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:06 N/A Reserved N/A N/A D05 R/W Mnth 0x0 Month 0 1 D04 R/W Date 0x0 Date 0 1 D03 R/W Hour 0x0 R/W Min 0x0 R/W Sec 0x0 R/W Hsec 0x0 Disable the minute event Enable the minute event Sec
..... REAL TIME CLOCK MODULE Event Flags register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved Register bit assignment 7 6 5 4 3 2 1 0 Alarm Mnth Evnt Date Evnt Hour Evnt Min Evnt Sec Evnt Hsec Evnt Bits Access Mnemonic Reset Description D31:07 N/A Reserved N/A N/A D06 R/R Alarm 0x0 Alarm event One of the events programmed in the Alarm Events register has triggered.
REAL TIME CLOCK MODULE Interrupt Enable register Interrupt Enable register .................................................................................. Address: 9006 0020 The Interrupt Enable register sets which events can generate and interrupt. The interrupt that is generated remains set until it is cleared by disabling the event or by reading/clearing the Event Flags register.
..... REAL TIME CLOCK MODULE Interrupt Disable register Interrupt Disable register .................................................................................. Address: 9006 0024 The Interrupt Disable register resets interrupts that are currently enables. An interrupt is disabled by writing a 1, then a 0, to the appropriate disable register bit.
REAL TIME CLOCK MODULE Interrupt Enable Status register Interrupt Enable Status register .................................................................................. Address: 9006 0028 The Interrupt Enable Status register determines which interrupt sources are enabled and which interrupt sources are disabled.
..... REAL TIME CLOCK MODULE General Status register General Status register .................................................................................. Address: 9006 002C The General Status register determines the status of the RTC configuration. If an invalid configuration is found, the RTC counters do not start operation.
REAL TIME CLOCK MODULE General Status register 472 Hardware Reference NS9215
Analog-to-Digital Converter (ADC) Module C H A P T E R 1 5 T he NS9215 ASIC supports a 12-bit successive approximation analog-to-digital converter (ADC). To maximize flexibility, an input pin is provided to apply an external reference voltage, which defines the full scale input range. An analog multiplexer is included to enable the selection of up to eight inputs.
ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE ADC DMA procedure vref ADC vref_gnd vin_7 vin_0 ADC Control .. . 8:1 MUX SAR ADC dout[11:0] done adc_clk adc_reset sel[2:0] start ADC control block The ADC control block provides access between the CPU and the ADC module. The ADC clock and control signals are generated in this block. The ADC module output can be either DMA’d to memory or read directly by the CPU.
..... ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE ADC control and status registers 2 Set up the ADC DMA control registers and buffer descriptors (UART channel D). 3 Reset the ADC module by writing a 0 then a 1 to bit 8 in the Module Reset register at address A090 0180. 4 Flush the ADC DMA FIFO by writing a 1 then a 0 to bit 17 in UART Channel D Wrapper Configuration register at address 9002 9000.
ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE ADC Configuration register Register 31 30 29 28 27 26 25 24 ADCEN 15 23 22 20 19 18 14 13 12 11 10 9 8 17 16 INSTAT Reserved 7 6 5 4 3 INTCLR DMAEN Reserved Register bit assignment 21 Bit(s) Access Mnemonic Reset Description D31 R/W ADCEN 0 0 1 2 1 0 SEL The ADC module is disabled and held in reset The ADC module is enabled D30:19 N/A Reserved N/A N/A D18:16 R INSTAT 0 Interrupt status Indicates the channel
..... ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE ADC Clock Configuration register ADC Clock Configuration register .................................................................................. Address: 9003_9004 The ADC Clock Configuration register controls the ADC clock generator. The source clock is the output of the PLL. The maximum ADC clock frequency is 14 MHz and the conversion time is 14 clock cycles.
ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE ADC Output Registers 0-7 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Not used 15 14 13 12 11 10 9 8 DOUT Not used Register bit assignment 478 7 Bit(s) Access Mnemonic Reset Description D31:12 R/W Not used 0 This field must be written to 0. D11:00 R DOUT 0 Provides the output of the ADC for each channel.
..... TIMING Electrical characteristics Timing C H A P T E R 1 6 T his chapter provides the electrical specifications, or timing, integral to the operation of the processor. Timing includes information about DC and AC characteristics, output rise and fall timing, and crystal oscillator specifications. Electrical characteristics .................................................................................. Absolute maximum ratings The processor operates at a 1.8V core, with 3.
TIMING Electrical characteristics Recommended operating conditions Recommended operating conditions specify voltage and temperature ranges over which a circuit’s correct logic function is guaranteed. The specified DC electrical characteristics are satisfied over these ranges. Below are the recommended operating conditions. Symbol a Parameter DC supply voltage Maximum junction temperature Rating Unit VDDA 3.0 to 3.6 V VDDC (core) 1.62 to 1.98 V TJ 125 o C a VDDA: Ratings of I/O cells for 3.
..... TIMING DC electrical characteristics DC electrical characteristics .................................................................................. DC characteristics specify the worst-case DC electrical performance of the I/O buffers that are guaranteed over the specified temperature range. Inputs All electrical inputs are 3.3V interface. The processor I/O are 5 volt tolerant. DC electrical inputs are provided below.
TIMING Reset and edge sensitive input timing requirements Ouputs All electrical outputs are 3.3V interface. DC electrical outputs are provided below. Sym Parameter Value Unit VOH High-level output voltage (LVTTL level) Min VDDA-0.6 V VIL Low-level input voltage: LVTTL level Max 0.4 V Reset and edge sensitive input timing requirements .................................................................................. The critical timing requirement is the rise and fall time of the input.
..... TIMING Reset and edge sensitive input timing requirements If an external device driving the reset or edge sensitive input on a Digi processor cannot meet the 500ns maximum rise and fall time requirement, the signal must be buffered with a Schmitt trigger device. Here are sample Schmitt trigger device part numbers: www.digiembedded.
TIMING Memory Timing Memory Timing .................................................................................. All AC characteristics are measured with 35pF, unless otherwise noted. Memory timing contains parameters and diagrams for both SDRAM and SRAM timing. The table below describes the values shown in the SDRAM timing diagrams. Parm Description Min Max Unit M1 data input setup time to rising 1.0 ns M2 data input hold time to rising 0.
..... TIMING Memory Timing SDRAM burst read (16-bit) pr e a ct r ea d lat d -A d -B d -C d -D d- E d- F d -G d- H c l k _ ou t M2 M1 d a ta< 3 1:1 6 > M1 1 M4 ad dr N ot e- 1 N o te- 2 M5 d a ta _m as k < 3 : 0 > M6 d y _c s _ n< 3: 0> * M7 ra s _ n M8 c a s _n M9 we _ n Notes: www.digiembedded.com 1 This is the bank and RAS address. 2 This is the CAS address.
TIMING Memory Timing SDRAM burst read (16 bit), CAS latency = 3 pr e ac t r ea d la t la t d- A d- B c lk _ ou t M2 M1 da ta< 3 1:1 6> M1 1 M4 ad dr N ote - 1 N ote -2 M5 d ata _m as k< 3: 0> M6 d y _c s _ n< 3: 0> * M7 ra s _n M8 c a s _n M9 we _n Notes: 486 1 This is the bank and RAS address. 2 This is the CAS address.
..... TIMING Memory Timing SDRAM burst write (16 bit) pr e ac t w r d- A d -B d -C d- D d -E d -F d- G d -H c lk _ ou t M 12 M1 0 d a ta < 3 1 : 0 > M4 N o te -1 ad dr N o te -2 M5 d a ta _ m a s k < 3 : 2 > M5 d a ta _ m a s k < 1 :0 > * M6 d y _c s _ n< 3: 0> * M7 ra s _ n M8 c a s _n M9 we _n Notes: www.digiembedded.com 1 This is the bank and RAS address. 2 This is the CAS address.
TIMING Memory Timing SDRAM burst read (32 bit) pr ec h g ac t iv e re ad c a s lat da ta -A dat a- B c lk _ ou t M2 M1 d ata < 31: 0> M4 M 11 N ote -1 ad dr No te- 2 M5 da ta_ m as k < 3:0 >* M6 d y _c s _ n< 3: 0> * M7 ra s _n M8 c a s _n M9 we _n Notes: 488 1 This is the bank and RAS address. 2 This is the CAS address.
..... TIMING Memory Timing SDRAM burst read (32 bit), CAS latency = 3 p re a ct re ad lat la t da ta- A d ata - B da ta- C d ata -D c lk_ ou t M2 M1 d ata < 31: 0> M4 M1 1 N o te- 1 ad dr N o te- 2 M5 da ta_ m as k < 3:0 >* M6 d y _c s_ n< 3: 0> * M7 ra s _n M8 c a s _n M9 we _n Notes: www.digiembedded.com 1 This is the bank and RAS address. 2 This is the CAS address.
TIMING Memory Timing SDRAM burst write (32-bit) prechg ac ti ve w r d-A data-B cl k_out M10 M12 data<31:0> M4 N ote- 1 addr N ote- 2 M5 dat a_mask <3:0>* M6 dy_c s_n<3:0> M7 ras _n M8 c as _n M9 w e_n Notes: 490 1 This is the bank and RAS address. 2 This is the CAS address.
..... TIMING Memory Timing SDRAM load mode clk_o ut M5 dy_ cs_n<3 :0> * M7 ras_ n M8 cas_ n M9 w e_ n M4 a dd r<11 :0 > op cod e SD L www.digiembedded.
TIMING Memory Timing SDRAM refresh mode clk_o ut M6 dy_ cs0_ n M6 dy_ cs1_ n M6 dy_ cs2_ n M6 dy_ cs3_ n M7 ras_ n M8 cas_ n M9 we_ n 492 Hardware Reference NS9215
..... TIMING Memory Timing Clock enable timing clk_out M3 M14 clk_en<3:0> M13 SDRAM cycle clk_enable.td www.digiembedded.
TIMING Memory Timing Values in SRAM timing diagrams The next table describes the values shown in the SRAM timing diagrams.
..... TIMING Memory Timing Static RAM read cycles with 0 wait states c lk _ ou t M 26 M2 5 d ata < 31: 0> M1 7 M 18 ad dr < 27: 0> M1 9 M 20 M2 7 M 28 M2 3 M 24 s t_c s _ n< 3: 0> oe _n by te _lan e< 3: 0> S t ti R AM d l WTRD = 1 WOEN = 0 If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16bit, and 8-bit read cycles. If the PB field is set to 0, the byte_lane signal will always be high. static_rd_0wt.mif www.digiembedded.
TIMING Memory Timing Static RAM asynchronous page mode read, WTPG = 1 N ot e- 1 N o te- 2 N o te- 2 N o te- 2 c lk _ ou t M2 6 M 26 M25 M2 5 d ata < 31: 0> M1 7 M 18 N ote -3 ad dr < 27: 0> N ote -4 M 18 N ot e- 5 No te- 6 M1 9 M 20 M2 7 M 28 M2 3 M 24 s t_c s _ n< 3: 0> oe _n by te _lan e< 3: 0> N o te- 7 WTPG = 1 WTRD = 2 If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-bit, and 8-bit read cycles.
..... TIMING Memory Timing Static RAM read cycle with configurable wait states clk_ ou t M 26 M 25 d ata < 31: 0> M 17 M1 8 ad dr< 27: 0> M 19 M 20 N ote -1 st_cs_ n<3: 0> M 27 M 28 N ote -1 oe _n M 23 byte _lan e<3: 0> M 24 N ote -1 WTRD = from 1 to 15 WOEN = from 0 to 15 If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-bit, and 8-bit read cycles. If the PB field is set to 0, the byte_lane signal will always be high. www.digiembedded.
TIMING Memory Timing Static RAM sequential write cycles clk_ ou t M 15 M 16 M 17 M 18 M 19 M 20 d ata < 31: 0> ad dr< 27: 0> st_cs_ n< 3: 0> M2 1 M 22 we _n M 23 M 24 byte _lan e< 3: 0> M2 1 byte _lan e[ 3:0 ] a s WE * M 22 N ot e1 WTWR = 0 WWEN = 0 During a 32-bit transfer, all four byte_lane signals will go low. During a 16-bit transfer, two byte_lane signals will go low. During an 8-bit transfer, only one byte_lane signal will go low.
..... TIMING Memory Timing Static RAM write cycle clk_ ou t M 15 M16 M 17 M18 M 19 M20 d ata < 31: 0> ad dr< 27: 0> st_cs_ n< 3: 0> M 21 M22 we _n M 23 M24 byte _lan e< 3: 0> M 21 byte _lan e[ 3:0 ] a s WE * M22 N ot e- 1 WTWR = 0 WWEN = 0 During a 32-bit transfer, all four byte_lane signals will go low. During a 16-bit transfer, two byte_lane signals will go low. During an 8-bit transfer, only one byte_lane signal will go low.
TIMING Memory Timing Static write cycle with configurable wait states c lk _ ou t M15 M 16 M17 M 18 d ata < 31: 0> ad dr < 17: 0> M19 M 20 N ote - 1 s t_c s _ n< 3: 0> M 21 M 22 N ote -2 we _n M23 M 24 N ote -3 by te _lan e< 3: 0> M 21 by te _lan e[ 3:0 ] a s W E * N ot e- 4 M 22 N ote -5 WTWR = from 0 to 15 WWEN = from 0 to 15 The WTWR field determines the length on the write cycle. During a 32-bit transfer, all four byte_lane signals will go low.
..... TIMING Memory Timing Slow peripheral acknowledge timing www.digiembedded.com The table below describes the values shown in the slow peripheral acknowledge timing diagrams.
TIMING Memory Timing Slow peripheral acknowledge read 0n s 50 ns 10 0n s 15 0n s 20 0n s clk_o ut M3 2 M2 6 da ta<3 1:0> M1 7 M1 8 ad dr <27 :0 > M2 0 M1 9 M3 1 st_cs_ n<3 :0 > M2 7 M2 8 M2 3 M2 4 oe _n byte _la n e<3:0 > M2 9 M3 0 ta_ str b Slow peripheral acknowledge write 0ns 50ns 100ns 150ns 200ns clk_out M15 M16 M17 M18 data<31:0> addr<27:0> M20 M19 M31 st_cs_n<3:0> M21 M22 we_n M23 M24 byte_lane<3:0> 3 M29 ta_strb 502 Hardware Reference NS9215 M30 6
..... TIMING Memory Timing Ethernet timing All AC characteristics are measured with 10pF, unless otherwise noted. The table below describes the values shown in the Ethernet timing diagrams.
TIMING Memory Timing I 2 C timing All AC characteristics are measured with 10pF, unless otherwise noted. The table below describes the values shown in the I2C timing diagram. Fast Mode Min Parm Description Min C1 iic_sda to iic_scl START hold time 4.0 0.6 µ C2 iic_scl low period 4.7 1.3 µ C3 iic_scl high period 4.7 1.3 µ C4 iic_scl to iic_sda DATA hold time 0 0 µ C5 iic_sda to iic_scl DATA setup tim 250 100 µ C6 iic_scl to iic_sda STA 4.7 0.
..... TIMING Memory Timing SPI Timing All AC characteristics are measured with 10pF, unless otherwise noted. The next table describes the values shown in the LCD timing diagrams.
TIMING Memory Timing Parm Description Min SP22 SPI enable low hold from last SPI CLK in falling SP23 Max Unit Mod es Not es 15 ns 0,3 1 SPI enable low hold from last SPI CLK in rising 15 ns 1,2 1 SP24 SPI CLK in high time SP26*40% SP26*60% ns 0,1,2, 5 3 SP25 SPI CLK in low time SP26*40% SP26*60% ns 0,1,2, 5 3 SP26 SPI CLK in period TBCLK*8 ns 0,1,2, 3 Notes: 1 Active level of SPI enable is inverted (that is, 1) if the CSPOL bit in Serial Channel Control Register B is s
..... TIMING Memory Timing SPI master mode 0 and 1: 2-byte transfer SP0 SP3 SP13 SP12 S9 SPI CLK Out (Mode 0) SP1 SP5 S10 SPI CLK Out (Mode 1) SPI Enable SP7 SPI Data Out MSB LSB SP4 LSB MSB LSB SP6 MSB SPI Data In SP8 MSB LSB Note: SPI data can be reversed such that LSB is first. Use the BITORDER bit in Serial Channel B/A/C/D Control Register A.
TIMING Memory Timing SPI slave mode 0 and 1: 2-byte transfer SP0 SP3 SP13 SP12 S9 SPI CLK Out (Mode0) SP1 SP5 S10 SPI CLK Out (Mode1) SPI Enable SP7 SPI Data Out MSB LSB SP4 MSB LSB MSB LSB SP6 MSB SPI Data In SP8 LSB Note: SPI data can be reversed such that LSB is first. Use the BITORDER bit in Serial Channel B/A/C/D Control Register A.
..... TIMING Reset and hardware strapping timing Reset and hardware strapping timing .................................................................................. All AC characteristics are measured with 10pF, unless otherwise noted. The next table describes the values shown in the IEEE 1284 timing diagram. Parm Description Min R1 reset_n minimum time 10 R2 reset_n to reset_done Typ NOR flash: 4.
TIMING JTAG timing JTAG timing .................................................................................. All AC characteristics are measured with 10pF, unless otherwise noted. The next table describes the values shown in the JTAG timing diagram. Parm Description Min Max J1 tms (input) setup to tck rising 5 ns J2 tms (input) hold to tck rising 2 ns J3 tdi (input) setup to tck rising 5 ns J4 tdi (input) hold to tck rising 2 ns J5 tdo (output) to tck falling 2.
..... TIMING Clock timing Clock timing .................................................................................. All AC characteristics are measured with 10pF, unless otherwise noted. System PLL reference clock timing Parm Description Min Max Unit SC1 x1_sys_osc cycle time 25 50 ns SC2 x1_sys_osc high time (SC1/2) x 0.45 (SC1/2) x 0.55 ns SC3 x1_sys_osc low time (SC1/2) x 0.45 (SC1/2) x 0.55 ns Notes The diagram below pertains to clock timing.
TIMING Clock timing 512 Hardware Reference NS9215
Packaging C H A P T E R 1 7 B elow is the processor package, 265 LF-XBGA. Diagrams that follow show the processor dimensions: top, bottom, and side views. Package ..................................................................................
PACKAGING Processor Dimensions Processor Dimensions ..................................................................................
..... PACKAGING Processor Dimensions www.digiembedded.
PACKAGING Processor Dimensions 516 Hardware Reference NS9215
Change log C H A P T E R 1 8 T he following changes were made since the last revision of this document. Revision B .................................................................................. Modified ADC data in the POR table. Added RTC clock and battery back up connection information. Updated POR and battery backup logic information for situations when the POR feature is not used. Added power dissipation data for 75MHz. Deleted IDDS because it does not apply to this type of IC.
